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首页 > Products > Power Management > Regulator > DDR terminal voltage regulator >2A Sink/Source Bus Termination Regulator CXTP65162 CXTP65161 CXTP65160 is a simple cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate
2A Sink/Source Bus Termination Regulator CXTP65162 CXTP65161 CXTP65160 is a simple cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate

The CXTP65162 CXTP65161 CXTP65160 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the REFEN pin voltage. The CXTP65162 CXTP65161 CXTP65160 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient.

2A Sink/Source Bus Termination Regulator CXTP65162 CXTP65161 CXTP65160 is a simple cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate
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1.产品概述       2.产品特点     84D嘉泰姆

3.应用范围       4.技术规格书下载(PDF文档)84D嘉泰姆

5.产品封装       6.电路原理图  84D嘉泰姆

7.相关产品84D嘉泰姆

   产品概述 返回TOP84D嘉泰姆


The CXTP65162 CXTP65161 CXTP65160 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the REFEN pin voltage. The CXTP65162 CXTP65161 CXTP65160 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The CXTP65162 CXTP65161 CXTP65160 are available in the PSOP-8 (Exposed Pad) surface mount packages.

   产品特点 返回TOP84D嘉泰姆


 Ideal for DDR-I, DDR-II and DDR-III VTT Applications 84D嘉泰姆

 Sink and Source 2A Continuous Current 84D嘉泰姆

 Integrated Power MOSFETs 84D嘉泰姆

 Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces. 84D嘉泰姆

 High Accuracy Output Voltage at Full-Load 84D嘉泰姆

 Output Voltage traces REFEN Pin Voltage. 84D嘉泰姆

 Low External Component Count 84D嘉泰姆

 Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output 84D嘉泰姆

 Current Limiting Protection 84D嘉泰姆

 Thermal Shutdown Protection 84D嘉泰姆

 PSOP-8 with exposed pad Pb-Free Package.84D嘉泰姆

   应用范围 返回TOP84D嘉泰姆


 Desktop PCs, Notebooks, and Workstations 84D嘉泰姆

 Graphics Card Memory Termination 84D嘉泰姆

 Set Top Boxes, Digital TVs, Printers 84D嘉泰姆

 Embedded Systems 84D嘉泰姆

 Active Termination Buses 84D嘉泰姆

 DDR-I, DDR-II and DDR-III Memory Systems84D嘉泰姆

   技术规格书(产品PDF) 返回TOP 84D嘉泰姆


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产品封装图 返回TOP84D嘉泰姆


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电路原理图 返回TOP84D嘉泰姆


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DDR Bus Termination Regulator(DDR总线终端稳压器)  84D嘉泰姆

Product84D嘉泰姆

Status 84D嘉泰姆

Output Offset Voltage84D嘉泰姆

Load Reg.84D嘉泰姆

Max Sink& Source Current 84D嘉泰姆

VIN    Max84D嘉泰姆

Control Voltage Range84D嘉泰姆

CXTP6516084D嘉泰姆

NRFND 84D嘉泰姆

±20mV 84D嘉泰姆

0.8%,1.2% 84D嘉泰姆

 3A84D嘉泰姆

6V 84D嘉泰姆

3.3V to   6V 84D嘉泰姆

CXTP6516184D嘉泰姆

Active 84D嘉泰姆

±20mV84D嘉泰姆

0.50%84D嘉泰姆

 1.584D嘉泰姆

6V84D嘉泰姆

3.3V  to 6V 84D嘉泰姆

CXTP6516284D嘉泰姆

Active 84D嘉泰姆

±20mV 84D嘉泰姆

0.50%84D嘉泰姆

 2A84D嘉泰姆

6V84D嘉泰姆

3.3V to   6V 84D嘉泰姆