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• 1.产品概述       2.产品特点     sAG嘉泰姆

• 3.应用范围       4.技术规格书下载（PDF文档）sAG嘉泰姆

• 5.产品封装       6.电路原理图  sAG嘉泰姆

• 7.相关产品sAG嘉泰姆

   产品概述 返回TOPsAG嘉泰姆

TheCX24C512 CX24C512G are EEPROM devices that use the industrial standard 2-wire interface for communications. The CX24C512 CX24C512G contains a memory array of 512K-bits (65,536x8), which is organized in 128-byte per page. The EEPROM can operate in a wide voltage range from 1.7V to 5.5V which fits most application. This product can provide a low-power 2-wire EEPROM solution. The device is offered in Lead-free, RoHS, halogen free or Green. The available package types are 8-pin SOIC/SOP, TSSOP, DFN and CSP. The CX24C512 CX24C512Gis compatible with the industrial standard 2-wire bus protocol. If in case the bus is not responded, a new sent Op-code command will reset the bus and the device will respond correctly. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Utilizing such bus protocol, a Master device, such as a microcontroller, can usually control one or more Slave devices, alike this CX24C512G The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The CX24C512Galso has a Write Protect pin (WP) to allow blocking any write operations over specified memory area. Under no circumstance, the device will be hung up. In order to refrain the state machine entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is embedded. During power-up, the device does not respond to any instructions until the supply voltage (VCC) has reached an acceptable stable level above the reset threshold voltage. Once VCC passes the power on reset threshold, the device is reset and enters into the Standby mode. This would also avoid any inadvertent Write operations during power-up stage. During power-down process, the device will enter into standby mode, once VCC drops below the power on reset threshold voltage. In addition, the device will be in standby mode after receiving the Stop command, provided that no internal write operation is in progress. Nevertheless, it is illegal to send a command unless the VCC is within its operating level.

   产品特点 返回TOPsAG嘉泰姆

 Two-Wire Serial Interface, I2C TM Compatible sAG嘉泰姆

– Bi-directional data transfer protocol sAG嘉泰姆

 Wide-voltage Operation – VCC = 1.7V to 5.5V sAG嘉泰姆

 Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V) sAG嘉泰姆

 Standby current (max.): 1A, 1.7V sAG嘉泰姆

 Operating current (max.): 2 mA, 1.7V sAG嘉泰姆

 Hardware Data Protection – Write Protect Pin sAG嘉泰姆

 Sequential & Random Read Features sAG嘉泰姆

 Memory organization: 65,536 x 8 bits sAG嘉泰姆

 Page Size: 128 bytes sAG嘉泰姆

 Page write mode sAG嘉泰姆

– Up to 128 bytes per page write sAG嘉泰姆

 Self timed write cycle with auto clear: 5ms (max.) sAG嘉泰姆

 Filtered inputs for noise suppression sAG嘉泰姆

 High-reliability sAG嘉泰姆

– Endurance: 1 million cycles sAG嘉泰姆

– Data retention: 100 years sAG嘉泰姆

 Industrial temperature grades sAG嘉泰姆

 Packages: SOIC/SOP, TSSOP, DFN and CSP sAG嘉泰姆

 Lead-free, RoHS, Halogen free, GreensAG嘉泰姆

   应用范围 返回TOPsAG嘉泰姆

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   技术规格书（产品PDF) 返回TOP sAG嘉泰姆

     需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！sAG嘉泰姆

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产品封装图 返回TOPsAG嘉泰姆

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电路原理图 返回TOPsAG嘉泰姆

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