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首页 > Products > MCU Memory ADC Clock  > ADC > Logical Circuit Comparator >1-2-4-Bit Bidirectional Voltage-Level Translator with Automatic Direction Sensing and ?5kV ESD CXCO4332 is designed so that the EO input circuit is supplied by VCCA This device is fully specified
1-2-4-Bit Bidirectional Voltage-Level Translator with Automatic Direction Sensing and ?5kV ESD CXCO4332 is designed so that the EO input circuit is supplied by VCCA This device is fully specified

This 4-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5V voltage nodes. VCCA should not exceed VCCB. When the enable-output (EO) input is low, all outputs are placed in the high-impedance state

1-2-4-Bit Bidirectional Voltage-Level Translator with Automatic Direction Sensing and ?5kV ESD CXCO4332 is designed so that the EO input circuit is supplied by VCCA This device is fully specified
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1.产品概述       2.产品特点     Paz嘉泰姆

3.应用范围       4.技术规格书下载(PDF文档)Paz嘉泰姆

5.产品封装       6.电路原理图  Paz嘉泰姆

7.相关产品Paz嘉泰姆

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This 4-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5V voltage nodes. VCCA should not exceed VCCB. When the enable-output (EO) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state during power up or power down, EO should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The CXCO4332 is designed so that the EO input circuit is supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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„ 1.2V to 3.6V on A port and 1.65V to 5.5V on B port (VCCA ≤ VCCB) Paz嘉泰姆

„ VCC Isolation Feature-If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State Paz嘉泰姆

„ EO Input Circuit Referenced to VCCA Paz嘉泰姆

„ Low Power Consumption, 5μA Max ICC Paz嘉泰姆

„ No Power-Supply Sequencing Required-Either VCCA or VCCB Can be Ramped First Paz嘉泰姆

„ Ioff Supports Partial-Power-Down Mode Operation Paz嘉泰姆

„ Latch-Up Performance Exceeds 100mA Per JESD 78, Class II Paz嘉泰姆

„ ESD Protection Exceeds JESD 22 – A Port 2500V Human-Body Model (A114-B) 1500V Charged-Device Model (C101) – B Port ±15kV Human-Body Model (A114-B) 1500V Charged-Device Model (C101) Paz嘉泰姆

„ SC-70-6 (SOT-363), SOT-23-6, SOT-23-8, AQFN1.7X2.0-12 and AQFN1.5X1.5-8 PackagePaz嘉泰姆

   应用范围 返回TOPPaz嘉泰姆


   aPaz嘉泰姆

   技术规格书(产品PDF) 返回TOP Paz嘉泰姆


     需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持!Paz嘉泰姆

 QQ截图20160419174301.jpgPaz嘉泰姆

产品封装图 返回TOPPaz嘉泰姆


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电路原理图 返回TOPPaz嘉泰姆


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