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首页 > Products > MCU Memory ADC Clock  > Real Time Clock >The CXCL3471BC5 series are high frequency low power consumption PLL clock generator ICs with divider circuit & multiplier PLL circuit Laser trimming gives the option of being able to select
The CXCL3471BC5 series are high frequency low power consumption PLL clock generator ICs with divider circuit & multiplier PLL circuit Laser trimming gives the option of being able to select

Output frequency (Q0) is equal to reference oscillation (fCLKin) multiplied by N/M, within a range of 3MHz to 30MHz. Q1 output is selectable from input reference frequency (f0), input reference frequency/2 (f0/2), ground (GND), and comparative frequency (f0/M). Further, comparative frequencies, within a range of 12KHz to 500KHz, can be obtained by dividing the reference oscillatio

The CXCL3471BC5 series are high frequency low power consumption PLL clock generator ICs with divider circuit & multiplier PLL circuit Laser trimming gives the option of being able to select
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    CXCL3471BC5系列是以高频, 低消耗电流工作,内置分频, 倍频电,路的超小型封装PLL时钟发生器。内置有分频电路, 倍频PLL电路。能够用微调技术从1,3~2047的分频因子(M),以及6~2047的倍频因子(N)中选择任意值。相对于主时钟(fCLKin)的输出频率Q0为:Q0=fCLKin×N//M。输出频率范围为3MHz~30MHz。Q1端的输出可从主时钟, GND, 比较频率/2, PLL输出频率/2中进行选择。对主时钟信号可输入14kHz~35MHz的基准时钟信号。将该主时钟分频,生成比较频率。比较频率范围为12kHz~500kHz。能够通过CE端停止振荡,减少消耗电流。此时,输出处于高阻抗状态。The CXCL3471BC5 series are high frequency, low power consumption PLL clock generator ICs with divider circuit & multiplier PLL circuit. Laser trimming gives the option of being able to select from divider ratios (M) of 1,3 to 2047 and multiplier ratios (N) of 6 to 2047. Output frequency (Q0) is equal to reference oscillation (fCLKin) multiplied by N/M, within a range of 3MHz to 30MHz. Q1 output is selectable from input reference frequency (f0), input reference frequency/2 (f0/2), ground (GND), and comparative frequency (f0/M). Further, comparative frequencies, within a range of 12KHz to 500KHz, can be obtained by dividing the reference oscillatioeoC嘉泰姆

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