Product Overview

            CXBD3566 is oneCost-effective dual-channel high-speed driver chipDesigned for new energy and industrial power system. ItsIndependent enable control (ENA/ENB)The function can realize accurate start and stop management of two-way drives, and is suitable for complex scenarios such as H-bridge motor control and interleaved DCDC topology. The chip has built-in logic signal processing and level shifting circuit, supporting a wide logic input range of-6v ~ 25V, which can effectively suppress the back electromotive force of the motor or the interference of switching noise. Single channel output under 5V-25V power supplyAsymmetric 5A/4A drive current, quickly drive MOSFETs, IGBTs, and third-generation semiconductor devices (such as GaN/SiC). Dual-Channel delay matching technology ensures strict synchronization of multiple signals and is suitable for time series sensitive applications such as high-frequency inverter and LLC resonant power supplies. The SOP8 package combines optimized heat dissipation design to meet the layout requirements of high-density PCB.ruS嘉泰姆

   Core features ruS嘉泰姆

   Dual-Channel independent control: the two drive signals are completely isolated and can be independently enabled and controlled by ENA/ENB, which can flexibly adapt to multi-scenario drive requirements.ruS嘉泰姆

• Industrial voltage compatibility:ruS嘉泰姆

  • VDD power supply range 5V-25V, logic input withstand voltage-6V to 25V, anti-negative pressure interferenceruS嘉泰姆

  • Built-in VDD undervoltage protection (UVLO) to prevent abnormal voltage damage to the systemruS嘉泰姆

• High precision driving performance:ruS嘉泰姆

  • Single Channel peak current 5A (pull)/4A (fill), support SiC/GaN and other high frequency device drivingruS嘉泰姆

  • Dual-Channel delay matching ≤ 10ns to ensure synchronous control accuracyruS嘉泰姆

• Extreme dynamic response:ruS嘉泰姆

  • Input-to-output propagation delay <30ns, rise/failling edge time ≤ 15ns, optimized switching lossruS嘉泰姆

• Anti-interference design:ruS嘉泰姆

  • INA/INB channel built-in 400 Kohm pull-down resistor, ENA/ENB integrated 200 Kohm pull-up resistorruS嘉泰姆

  • Force OUTA/OUTB low level when the input is suspended to prevent false triggering of power tuberuS嘉泰姆

• Energy saving and integration advantages:ruS嘉泰姆

  • Static power consumption <200μa, support low power consumption scenarios such as battery/solar energyruS嘉泰姆

  • The SOP8 package is compatible with industry standards and supports full temperature range operation from-40 ℃ to 125 ℃.ruS嘉泰姆

   Typical application scenarios ruS嘉泰姆

   Photovoltaic/energy storage inverter: Dual-Channel Drive H-bridge topology to improve MPPT dynamic responseruS嘉泰姆

Industrial Motor Drive: support BLDC/PMSM motor forward and reverse rotation and brake controlruS嘉泰姆

GaN/SiC driving scheme: 5A peak current adaptation 650V/1200V power moduleruS嘉泰姆

Polyphase DCDC converter: enable independent control to realize interleaving switch to reduce input rippleruS嘉泰姆

Intelligent solar controller: wide pressure design compatible with 12V/24V/48V battery systemruS嘉泰姆

High frequency switching power supply: drive synchronous rectification MOS tube, improve conversion efficiency to 95% +ruS嘉泰姆

   Technical Specification (product PDF)ruS嘉泰姆

For detailed PDF specifications, please scan WeChat and contact us. You can also get free samples and technical support.!ruS嘉泰姆

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   Product packaging diagramruS嘉泰姆

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Application DescriptionruS嘉泰姆

        In switching power supply applications, high current gate drive equipment is required for various reasons. In order to realize fast switching of power equipment and reduce phaseruS嘉泰姆
With off switching power loss, the powerful Gate Drive chip can be used between the PWM output of the control device and the gate of the power semiconductor device.ruS嘉泰姆
When the PWM controller cannot directly drive the power device, the gate drive chip becomes indispensable. With the emergence of digital power supply, this kindruS嘉泰姆
The situation will often occur because the PWM signal from the digital controller is usually a 3.3V logic signal, which is not enough to effectively turn on a job.ruS嘉泰姆
Rate Switch. A level shift circuit is required to boost the 3.3V signal to the gate drive voltage (such as 12V) to fully open power tube and minimizeruS嘉泰姆
Conduction loss. Traditional buffer driver circuits based on the NPN/PNP bipolar transistor in the totem pole configuration, due to their lack of level conversion capability,ruS嘉泰姆
Therefore, it is not enough to use in digital power supply. The gate driver chip effectively combines level shifting and buffer driving functions. In general, the gateruS嘉泰姆
The driver chip is an extremely important component in switching power supply. It combines high performance, low cost, small number of components, reduced board space and simplified system.ruS嘉泰姆
Advantages of design.ruS嘉泰姆
Layout guideruS嘉泰姆

   In the high-current fast switching circuit, the correct PCB layout is very important, which can provide the stability of the design. CXBD3566 gate drive coreruS嘉泰姆
The chip has a short propagation delay and a strong output current, a smaller rising edge and a failling edge time. Peak power at higher VDD voltageruS嘉泰姆
The flow capability is even higher (5A peak current is at VDD = 12V). If the trace length and impedance are not well controlled, very high di/dtruS嘉泰姆
Unacceptable ringing occurs. When using these high-speed driver chips for design, we recommend that you use the following circuit layout guidelines.ruS嘉泰姆
• Keep the driver chip as close to the power device as possible to reduce the length of large current traces between the output pin and the power device gate.ruS嘉泰姆
• Close the VDD bypass capacitor to the driver chip as much as possible and minimize the trace length to improve the noise filtering effect. These capacitors are supported inruS嘉泰姆
The peak current drawn from VDD when the power device is turned on. We recommend that you use patch capacitor with low inductance.ruS嘉泰姆
• Enable and close the current loop path (drive chip, power device and VDD bypass capacitor) as much as possible to maintain minimum parasitismruS嘉泰姆
Inductance. During the Power Tube on and off transient, high dI/dt will be generated, which will be introduced on the output pin of the driver chip and the gate of the power device.ruS嘉泰姆
Significant voltage spikes.ruS嘉泰姆
• Where possible, the current input and output traces are parallel, using magnetic flux elimination.ruS嘉泰姆
• Separate power supply traces and signal traces, such as output and input signals.ruS嘉泰姆
• Star grounding is a good way to reduce the noise from one current loop coupling to another. The GND of the driver chip should be in a singleruS嘉泰姆
One point is connected to other circuit nodes, such as the source of power MOSFETs, the ground of PWM controllers, etc. The connection path should be as short as possible to reduce inductance,ruS嘉泰姆
And as wide as possible to reduce the resistance.ruS嘉泰姆
• Use ground layer to provide noise shielding. The fast rise and fall time at OUT may interfere with the input signal. The formation cannot be anyruS嘉泰姆
The conductive path of the current loop. On the contrary, the formation must be connected to the star through a single trace to establish the ground potential. In addition to the noise screenruS嘉泰姆
Outside the enclosure, ground connection can also help heat dissipation.ruS嘉泰姆
• In complex environments, ground CXBD3566 of the input of unused channels to VDD or GND to ensure normal output and prevent noise introductionruS嘉泰姆
Output failure.ruS嘉泰姆
Layout exampleruS嘉泰姆

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Relevant chip selection guide              More related products......ruS嘉泰姆