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首页 > Products > Audio Amplifier IC > Voice and Video Driver >CXAR41335 low-power audio codec - high fidelity ANC noise reduction, 38 μ s ultra-low latency | JTMIC official website
CXAR41335 low-power audio codec - high fidelity ANC noise reduction, 38 μ s ultra-low latency | JTMIC official website

CXAR41335 is a low-power audio codec that integrates four inputs and two outputs. It has a powerful digital signal processing engine and supports functions such as filtering, level control, signal mixing, and real-time monitoring. This chip supports single ended analog microphone input and up to four digital microphone inputs. The entire path from analog input to DSP core and then to analog output has been deeply optimized for low latency, making it particularly suitable for active noise reduction applications with strict requirements for audio quality, power consumption, and latency. Adopting QFN48 packaging, a complete headphone solution can be built with only a small number of peripheral components

CXAR41335 low-power audio codec - high fidelity ANC noise reduction, 38 μ s ultra-low latency | JTMIC official website
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CXAR41335: Breakthrough low-power audio codec, redefining high fidelity noise cancelling audio experienceUUv嘉泰姆

            In today's rapidly developing portable audio devices, consumers have higher requirements for audio quality, noise reduction effect, and battery life. CXAR41335, as a low-power codec designed specifically for high-end audio applications, integrates a high-performance audio processing engine, flexible input-output configuration, and advanced power management technology, providing a complete solution for applications such as active noise cancelling headphones and portable audio devices. This article will comprehensively analyze the technical features, system architecture, and design points of CXAR41335, helping developers create the next generation of audio products.UUv嘉泰姆


1、 Chip Overview: High Integration Audio Processing Platform

      CXAR41335 is a low-power audio codec that integrates four inputs and two outputs. It has a powerful digital signal processing engine and supports functions such as filtering, level control, signal mixing, and real-time monitoring. This chip supports single ended analog microphone input and up to four digital microphone inputs. The entire path from analog input to DSP core and then to analog output has been deeply optimized for low latency, making it particularly suitable for active noise reduction applications with strict requirements for audio quality, power consumption, and latency. Adopting QFN48 packaging, a complete headphone solution can be built with only a small number of peripheral components.UUv嘉泰姆


2、 Core Features and Advantages

2.1.  High performance audio processingUUv嘉泰姆

·    24 bit high-precision ADC and DAC, supporting 102dB SNR (PGA+ADC path) and 107dB combined signal-to-noise ratio;UUv嘉泰姆

·    Integrated dual second-order filter, limiter, volume control, and mixer, supporting fully programmable audio processing;UUv嘉泰姆

·    Ultra low latency architecture, with an analog-to-digital conversion delay of only 38 μ s, ensuring real-time noise reduction effect.UUv嘉泰姆

2.2.  Flexible interface configurationUUv嘉泰姆

·    Supports 4 single ended analog inputs (configurable as microphone or linear input);UUv嘉泰姆

·    Dual stereo digital microphone input, compatible with mainstream digital microphone solutions;UUv嘉泰姆

·    Stereo analog output supports single ended or differential mode, and can be configured as linear output or headphone driver.UUv嘉泰姆

2.3.  Wide range clock and sampling rateUUv嘉泰姆

·    The serial data port is compatible with I2S, left aligned, right aligned, and TDM modes;UUv嘉泰姆

·    The sampling rate supports 8kHz to 192kHz, meeting the full scene requirements from speech to high-resolution music;UUv嘉泰姆

·    Built in PLL and asynchronous sampling rate converter, supporting a full clock range of 8MHz to 27MHz.UUv嘉泰姆

2.5.  Advanced power managementUUv嘉泰姆

·    Multi voltage domain design: Analog and digital I/O support 1.8V-3.3V, DSP core supports 1.1V-1.8V;UUv嘉泰姆

·    A typical ANC solution has a power consumption of only 15mW, greatly extending the battery life of portable devices;UUv嘉泰姆

·    Supports multiple power-saving modes and can dynamically adjust power consumption strategies according to application scenarios.UUv嘉泰姆

2.6.  Dual control interfaceUUv嘉泰姆

·    Support I2C and SPI control interfaces, provide register configuration and DSP program loading;UUv嘉泰姆

·    Equipped with self starting mode, it can automatically load configuration parameters through external EEPROM.UUv嘉泰姆


3、 Internal architecture and signal pathways

The internal architecture of CXAR41335 includes three major modules: analog front-end, digital processing engine, and output driverUUv嘉泰姆

·    analog front-endFour single ended analog inputs equipped with programmable gain amplifiers, supporting microphone bias and linear input; The stereo ADC adopts a 24 bit high-precision architecture to ensure input signal quality.UUv嘉泰姆

·    Digital Processing EngineBuilt in programmable DSP core, supports parallel execution of 32 instructions, and implements processing such as filtering, mixing, volume control, and limiting; Support low latency direct path to meet real-time noise reduction requirements.UUv嘉泰姆

·    Output driverStereo DAC supports single ended or differential output and can directly drive headphone loads; Under 1.8V power supply, 32Ω The output power of the load reaches 8.4mW (single ended) or 32.5mW (differential).UUv嘉泰姆


4、 Key performance parameters

4.1.  Power CharacteristicsUUv嘉泰姆

·    AVDD/IOVDD:1.8V-3.3V,DVDD:1.1V-1.8V;UUv嘉泰姆

·    Typical working current: approximately 15.5mW at a sampling rate of 192kHz;UUv嘉泰姆

·    The power consumption in power-off mode is as low as 1μ W, greatly improving standby life.UUv嘉泰姆

4.2.  audio performanceUUv嘉泰姆

·    ADC dynamic range: 102dB (A-weighted);UUv嘉泰姆

·    DAC output: single ended 0.53Vrms (1.8V), differential 1.0Vrms (1.8V);UUv嘉泰姆

·    Earphone driver: 32Ω Output 32.5mW (differential, 1.8V) under load, THD+N<0.1%.UUv嘉泰姆

4.3.  Digital interfaceUUv嘉泰姆

·    Supports I2C (standard/fast mode) and SPI control interfaces;UUv嘉泰姆

·    The serial data port supports 2/4/8 channel TDM mode for easy system expansion.UUv嘉泰姆


5、 Typical application scheme

5.1.  Active noise cancelling headphonesUUv嘉泰姆
By utilizing the low latency characteristics of CXAR41335 and multiple microphone inputs, a feedforward/feedback hybrid noise reduction system is constructed, and an adaptive noise reduction algorithm is implemented through DSP to enhance the noise reduction effect and user experience.
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5.2.  Bluetooth audio deviceUUv嘉泰姆
As an audio co processor for Bluetooth SoC, it provides high-quality audio encoding, decoding, and sound processing, supporting high-definition audio transmission and low-power operation.
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5.3.  Personal navigation and digital photography equipmentUUv嘉泰姆
By utilizing its low power consumption and small size characteristics, it provides high-quality audio input and output capabilities for portable devices.
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Attention should be paid to the following during design:UUv嘉泰姆

·    It is recommended to use low-noise LDO for analog power supply and strengthen decoupling design;UUv嘉泰姆

·    The digital microphone clock needs to maintain low jitter to ensure sampling accuracy;UUv嘉泰姆

·    The headphone output wiring should be kept away from digital signals to reduce crosstalk.UUv嘉泰姆


6、 Key points of system design and debugging

6.1.  Clock system designUUv嘉泰姆
Recommend using a 12.288MHz crystal oscillator to generate the required clock in conjunction with on-chip PLL; If an external clock is used, a 12.288MHz or 24.576MHz clock signal can be directly input.
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6.2.  Power timing managementUUv嘉泰姆
AVDD should be powered on before or at the same time as IOVDD; When cutting off power, it is necessary to mute the output before turning off the power to avoid popping sounds.
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6.3.  Control interface configurationUUv嘉泰姆

·    I2C mode is the default control mode. To switch to SPI mode, the SS pin needs to be pulled down three times in a row;UUv嘉泰姆

·    In self starting mode, the chip can automatically load configurations from external EEPROM, simplifying system initialization.UUv嘉泰姆


7、 Packaging and Production Suggestions

        CXAR41335 is packaged in QFN48 and has a size of 6.0mm× 6.0mm× 0.75mm, The pin spacing is 0.4mm. There are exposed solder pads at the bottom of the package, and it is recommended to connect them to the ground layer through vias to improve heat dissipation performance and soldering reliability. As an electrostatic sensitive device, it is necessary to take comprehensive anti-static measures during production, welding, and operation.UUv嘉泰姆

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8、 Conclusion: Choosing JTMIC as the New Benchmark for Audio Technology

          CXAR41335 provides a powerful technological foundation for modern audio devices with its low power consumption, low latency, and high integration. Whether it's high-end noise cancelling headphones, Bluetooth audio devices, or various portable audio products, this chip can help developers achieve excellent audio performance and differentiated product experiences.UUv嘉泰姆

        As JTMIC(jtm-ic.com)We provide customers with comprehensive technical support, reference design, and original stock supply for the highly recommended audio codec chips. Welcome to visit the official website to learn more about product details and technical information, and work together with JTMIC to create a new future of audio technology!UUv嘉泰姆


9、 Download the relevant chip selection guide;                     More similar products ...UUv嘉泰姆

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