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首页 > Products > Power Management > DC/DC Step-Up Converter > DC Step-Up Converter >The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137-1) or five (CXSU63137-2)
The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137-1) or five (CXSU63137-2)

The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.
The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.
The amplifiers are ideal for VCOM and VGAMMA applications, with
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slew
rate. All inputs and outputs are rail-to-rail.
The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).

The CXSU63137  integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137-1) or five (CXSU63137-2)
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目录UZW嘉泰姆

1.产品概述                       2.产品特点UZW嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 UZW嘉泰姆
5.产品封装图                     6.电路原理图                   UZW嘉泰姆
7.功能概述                        8.相关产品UZW嘉泰姆

一,产品概述(General Description)         UZW嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.UZW嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.UZW嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, withUZW嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slewUZW嘉泰姆
rate. All inputs and outputs are rail-to-rail.UZW嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).UZW嘉泰姆
二.产品特点(Features)UZW嘉泰姆


· 2.6V to 6.5V Input Supply Range UZW嘉泰姆

· Current-Mode Step-Up Regulator UZW嘉泰姆

 - Fast Transient Response UZW嘉泰姆

 - 1.2MHz Fixed Operating Frequency UZW嘉泰姆

· ±1.5% High-Accuracy Output Voltage UZW嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET UZW嘉泰姆

· High Efficiency UZW嘉泰姆

· Low Quiescent Current (0.6mA Typical) UZW嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF UZW嘉泰姆

· High-performance Operational Amplifiers UZW嘉泰姆

 - ±150mA Output Short-Circuit CurrentUZW嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth UZW嘉泰姆

 - Rail-to-Rail Inputs/Outputs UZW嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs UZW嘉泰姆

· Over-Temperature Protection UZW嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) UZW嘉泰姆

· Lead Free Available (RoHS Compliant)UZW嘉泰姆

三,应用范围 (Applications)UZW嘉泰姆


    TFT LCD Displays for MonitorsUZW嘉泰姆
   TFT LCD Displays for Notebook ComputersUZW嘉泰姆
   Automotive DisplaysUZW嘉泰姆
四.下载产品资料PDF文档 UZW嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持UZW嘉泰姆

 QQ截图20160419174301.jpgUZW嘉泰姆

五,产品封装图 (Package)UZW嘉泰姆


blob.pngUZW嘉泰姆
blob.pngPin Function DescriptionUZW嘉泰姆

PinUZW嘉泰姆

NameUZW嘉泰姆

Function DescriptionUZW嘉泰姆

CXSU63137UZW嘉泰姆

CXSU63137-1UZW嘉泰姆

CXSU63137-2UZW嘉泰姆

1UZW嘉泰姆

SRCUZW嘉泰姆

SRCUZW嘉泰姆

SRCUZW嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. BypassUZW嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.UZW嘉泰姆

2UZW嘉泰姆

REFUZW嘉泰姆

REFUZW嘉泰姆

REFUZW嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum ofUZW嘉泰姆
0.22μFcapacitor closed to the pins.UZW嘉泰姆

3UZW嘉泰姆

AGNDUZW嘉泰姆

AGNDUZW嘉泰姆

AGNDUZW嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect toUZW嘉泰姆
power ground (PGND) underneath the IC.UZW嘉泰姆

4UZW嘉泰姆

PGNDUZW嘉泰姆

PGNDUZW嘉泰姆

PGNDUZW嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-upUZW嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of outputUZW嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog groundUZW嘉泰姆
(AGND) underneath the IC.UZW嘉泰姆

5UZW嘉泰姆

OUT1UZW嘉泰姆

OUT1UZW嘉泰姆

OUT1UZW嘉泰姆

Output of Operational-Amplifier 1UZW嘉泰姆

6UZW嘉泰姆

NEG1UZW嘉泰姆

NEG1UZW嘉泰姆

NEG1UZW嘉泰姆

Inverting Input of Operational-Amplifier 1UZW嘉泰姆

7UZW嘉泰姆

POS1UZW嘉泰姆

POS1UZW嘉泰姆

POS1UZW嘉泰姆

Non-inverting Input of Operational-Amplifier 1UZW嘉泰姆

8UZW嘉泰姆

NCUZW嘉泰姆

OUT2UZW嘉泰姆

OUT2UZW嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalUZW嘉泰姆
connected of CXSU63137.UZW嘉泰姆

9UZW嘉泰姆

NCUZW嘉泰姆

NEG2UZW嘉泰姆

NEG2UZW嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalUZW嘉泰姆
connected of CXSU63137.UZW嘉泰姆

10UZW嘉泰姆

ICUZW嘉泰姆

POS2UZW嘉泰姆

POS2UZW嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. InternalUZW嘉泰姆
connected to GND of CXSU63137UZW嘉泰姆

11UZW嘉泰姆

BGNDUZW嘉泰姆

BGNDUZW嘉泰姆

BGNDUZW嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)UZW嘉泰姆
underneath the IC.UZW嘉泰姆

12UZW嘉泰姆

NCUZW嘉泰姆

NCUZW嘉泰姆

POS3UZW嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internalUZW嘉泰姆
connected of CXSU63137/CXSU63137.UZW嘉泰姆

13UZW嘉泰姆

NCUZW嘉泰姆

NCUZW嘉泰姆

OUT3UZW嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.UZW嘉泰姆

14UZW嘉泰姆

SUPUZW嘉泰姆

SUPUZW嘉泰姆

SUPUZW嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. BypassUZW嘉泰姆
SUP to BGND with a 0.1μF capacitor.UZW嘉泰姆

15UZW嘉泰姆

NCUZW嘉泰姆

POS3UZW嘉泰姆

POS4UZW嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-invertingUZW嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.UZW嘉泰姆

16UZW嘉泰姆

NCUZW嘉泰姆

NEG3UZW嘉泰姆

NEG4UZW嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input ofUZW嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.UZW嘉泰姆

17UZW嘉泰姆

NCUZW嘉泰姆

OUT3UZW嘉泰姆

OUT4UZW嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output ofUZW嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.UZW嘉泰姆

18UZW嘉泰姆

ICUZW嘉泰姆

ICUZW嘉泰姆

POS5UZW嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connectedUZW嘉泰姆
to GND of CXSU63137/CXSU63137.UZW嘉泰姆

19UZW嘉泰姆

NCUZW嘉泰姆

NCUZW嘉泰姆

NEG5UZW嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connectedUZW嘉泰姆
of CXSU63137/CXSU63137.UZW嘉泰姆

20UZW嘉泰姆

NCUZW嘉泰姆

NCUZW嘉泰姆

OUT5UZW嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.UZW嘉泰姆

21UZW嘉泰姆

LXUZW嘉泰姆

LXUZW嘉泰姆

LXUZW嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductorUZW嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.UZW嘉泰姆

22UZW嘉泰姆

INUZW嘉泰姆

INUZW嘉泰姆

INUZW嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can rangeUZW嘉泰姆
from 2.6V to 6.5V.UZW嘉泰姆

23UZW嘉泰姆

FBUZW嘉泰姆

FBUZW嘉泰姆

FBUZW嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider fromUZW嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider withinUZW嘉泰姆
5mm of FB.UZW嘉泰姆

24UZW嘉泰姆

COMPUZW嘉泰姆

COMPUZW嘉泰姆

COMPUZW嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCUZW嘉泰姆
from COMP to AGND.UZW嘉泰姆

PinFunction DescriptionUZW嘉泰姆

PinUZW嘉泰姆

NameUZW嘉泰姆

Function DescriptionUZW嘉泰姆

CXSU63137UZW嘉泰姆

CXSU63137-1UZW嘉泰姆

CXSU63137-2UZW嘉泰姆

24UZW嘉泰姆

COMPUZW嘉泰姆

COMPUZW嘉泰姆

COMPUZW嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCUZW嘉泰姆
from COMP to AGND.UZW嘉泰姆

25UZW嘉泰姆

FBPUZW嘉泰姆

FBPUZW嘉泰姆

FBPUZW嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of aUZW嘉泰姆
resistive voltage-divider between the regulator output and AGND to set theUZW嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-dividerUZW嘉泰姆
close to the pin.UZW嘉泰姆

26UZW嘉泰姆

DRVPUZW嘉泰姆

DRVPUZW嘉泰姆

DRVPUZW嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channelUZW嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.UZW嘉泰姆

27UZW嘉泰姆

FBNUZW嘉泰姆

FBNUZW嘉泰姆

FBNUZW嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of aUZW嘉泰姆
resistive voltage-divider between the regulator output and REF to set theUZW嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-dividerUZW嘉泰姆
close to the pin.UZW嘉泰姆

28UZW嘉泰姆

DRVNUZW嘉泰姆

DRVNUZW嘉泰姆

DRVNUZW嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channelUZW嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.UZW嘉泰姆

29UZW嘉泰姆

DELUZW嘉泰姆

DELUZW嘉泰姆

DELUZW嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND toUZW嘉泰姆
set the high-voltage switch startup delay.UZW嘉泰姆

30UZW嘉泰姆

CTLUZW嘉泰姆

CTLUZW嘉泰姆

CTLUZW嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switchUZW嘉泰姆
between COM and SRC is on and the high-voltage switch between COM andUZW嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRCUZW嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL isUZW嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less thanUZW嘉泰姆
1.25V.UZW嘉泰姆

31UZW嘉泰姆

DRNUZW嘉泰姆

DRNUZW嘉泰姆

DRNUZW嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channelUZW嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceedUZW嘉泰姆
VSRC.UZW嘉泰姆

32UZW嘉泰姆

COMUZW嘉泰姆

COMUZW嘉泰姆

COMUZW嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow theUZW嘉泰姆
voltage on COM to exceed VSRC.UZW嘉泰姆

六.电路原理图UZW嘉泰姆
七,功能概述UZW嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:UZW嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.UZW嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.UZW嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.UZW嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.UZW嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.UZW嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.UZW嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-upUZW嘉泰姆
八,相关产品UZW嘉泰姆

Switching Regulator > Boost ConverterUZW嘉泰姆

 Part_No UZW嘉泰姆

PackageUZW嘉泰姆

Archi-tecture UZW嘉泰姆

Input UZW嘉泰姆

Voltage    UZW嘉泰姆

Max Adj.UZW嘉泰姆

Output UZW嘉泰姆

Voltage UZW嘉泰姆

Switch Current Limit (max) UZW嘉泰姆

Fixed UZW嘉泰姆

Output UZW嘉泰姆

Voltage  UZW嘉泰姆

Switching UZW嘉泰姆

Frequency UZW嘉泰姆

Internal Power   Switch UZW嘉泰姆

Sync. Rectifier UZW嘉泰姆

 

minUZW嘉泰姆

maxUZW嘉泰姆

minUZW嘉泰姆

maxUZW嘉泰姆

(A)UZW嘉泰姆

(V)UZW嘉泰姆

(kHz)UZW嘉泰姆

 

CXSU63133UZW嘉泰姆

SOT89UZW嘉泰姆

VM UZW嘉泰姆

0.9UZW嘉泰姆

5.5UZW嘉泰姆

2.5UZW嘉泰姆

5.5UZW嘉泰姆

0.5UZW嘉泰姆

1.8|2.6|2.8|3UZW嘉泰姆

|3.3|3.8|4.5|5UZW嘉泰姆

-UZW嘉泰姆

NoUZW嘉泰姆

YesUZW嘉泰姆

CXSU63134UZW嘉泰姆

MSOP8|TSSOP8UZW嘉泰姆

|SOP8UZW嘉泰姆

VMUZW嘉泰姆

2.5UZW嘉泰姆

5.5UZW嘉泰姆

2.5UZW嘉泰姆

-UZW嘉泰姆

-UZW嘉泰姆

-UZW嘉泰姆

200 ~ 1000UZW嘉泰姆

NoUZW嘉泰姆

NoUZW嘉泰姆

CXSU63135UZW嘉泰姆

TSSOP8|SOP-8PUZW嘉泰姆

VMUZW嘉泰姆

1UZW嘉泰姆

5.5UZW嘉泰姆

2.5UZW嘉泰姆

5UZW嘉泰姆

1UZW嘉泰姆

2.5|3.3UZW嘉泰姆

300UZW嘉泰姆

YesUZW嘉泰姆

YesUZW嘉泰姆

CXSU63136UZW嘉泰姆

SOP8UZW嘉泰姆

CMUZW嘉泰姆

3UZW嘉泰姆

40UZW嘉泰姆

1.25UZW嘉泰姆

40UZW嘉泰姆

1.5UZW嘉泰姆

-UZW嘉泰姆

33 ~ 100UZW嘉泰姆

YesUZW嘉泰姆

NoUZW嘉泰姆

CXSU63137UZW嘉泰姆

TQFN5x5-32UZW嘉泰姆

CMUZW嘉泰姆

2.5UZW嘉泰姆

6.5UZW嘉泰姆

2.5UZW嘉泰姆

18UZW嘉泰姆

3UZW嘉泰姆

NoUZW嘉泰姆

1200UZW嘉泰姆

YesUZW嘉泰姆

NoUZW嘉泰姆

CXSU63138UZW嘉泰姆

TSOT23-5UZW嘉泰姆

TDFN2x2-6UZW嘉泰姆

CMUZW嘉泰姆

2.5UZW嘉泰姆

6UZW嘉泰姆

2.5UZW嘉泰姆

20UZW嘉泰姆

2UZW嘉泰姆

-UZW嘉泰姆

1500UZW嘉泰姆

YesUZW嘉泰姆

NoUZW嘉泰姆

CXSU63139UZW嘉泰姆

TQFN4x4-6UZW嘉泰姆

TDFN3x3-12UZW嘉泰姆

CMUZW嘉泰姆

1.8UZW嘉泰姆

5.5UZW嘉泰姆

2.7UZW嘉泰姆

5.5UZW嘉泰姆

5UZW嘉泰姆

-UZW嘉泰姆

1.2UZW嘉泰姆

YesUZW嘉泰姆

YesUZW嘉泰姆

CXSU63140UZW嘉泰姆

SOT23-5UZW嘉泰姆

CMUZW嘉泰姆

2.5UZW嘉泰姆

6UZW嘉泰姆

2.5UZW嘉泰姆

32UZW嘉泰姆

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