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首页 > Products > Power Management > DC/DC Step-Down Converter > Buck Step-Down Converter >The CXSD62104 integrates dual step-down, constant-ontime, synchronous PWM controllers (that drives dual N-channel MOSFETs for each channel) and two low drop-out regulators as well as various
The CXSD62104 integrates dual step-down, constant-ontime, synchronous PWM controllers (that drives dual N-channel MOSFETs for each channel) and two low drop-out regulators as well as various

The CXSD62104 integrates dual step-down, constant-ontime, synchronous
PWM controllers (that drives dual N-channel MOSFETs for each channel) and
two low drop-out regulators as well as various protections into a chip.The PWM
controllers step down high voltage of a battery to generate low-voltage for NB
applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5V
by setting a resistive voltage-divider from VOUTx to GND.The linear regulators
provide 5V and 3.3V output for standby power supply. The linear regulators
provide up to 100mA output current. When the PWMx output voltage is higher
than LDOx bypass threshold, the related LDOx regulator is shut off and its
output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation.
The CXSD62104 provides excellent transient response and accurate DC
output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM),
the CXSD62104 provides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. The Forced-PWM mode works nearly
at constant frequency for low-noise requirements. The unique ultrasonic mode
maintains the switching frequency above 25KHz, which eliminates noise in audio applications.
The CXSD62104 is equipped with accurate sourcing cur-rent-limit, output
under-voltage and output over-voltage protections, being perfect for NB
applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current.
A soft-stop function actively discharges the output capaci-tors by the discharge

The CXSD62104 integrates dual step-down, constant-ontime, synchronous PWM controllers (that drives dual N-channel MOSFETs for each channel) and two low drop-out regulators as well as various
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Product introduction

目录fnq嘉泰姆

1.产品概述                       2.产品特点fnq嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 fnq嘉泰姆
5.产品封装图                     6.电路原理图                   fnq嘉泰姆
7.功能概述                        8.相关产品fnq嘉泰姆

一,产品概述(General Description)         fnq嘉泰姆

        The CXSD62104  integrates dual step-down, constant-ontime, synchronousfnq嘉泰姆

PWM controllers (that drives dual N-channel MOSFETs for each channel) andfnq嘉泰姆
two low drop-out regulators as well as various protections into a chip.The PWMfnq嘉泰姆
controllers step down high voltage of a battery to generate low-voltage for NBfnq嘉泰姆
applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5Vfnq嘉泰姆
by setting a resistive voltage-divider from VOUTx to GND.The linear regulatorsfnq嘉泰姆
provide 5V and 3.3V output for standby power supply. The linear regulatorsfnq嘉泰姆

provide up to 100mA output current. When the PWMx output voltage is higher fnq嘉泰姆

than LDOx bypass threshold, the related LDOx regulator is shut off and its fnq嘉泰姆

output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation.fnq嘉泰姆
     The CXSD62104 provides excellent transient response and accurate DC fnq嘉泰姆

output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM), fnq嘉泰姆

the CXSD62104 provides very high efficiency over light to heavy loads with fnq嘉泰姆

loading-modulated switching frequencies. The Forced-PWM mode works nearly fnq嘉泰姆

at constant frequency for low-noise requirements. The unique ultrasonic modefnq嘉泰姆

 maintains the switching frequency above 25KHz, which eliminates noise in audio applications.fnq嘉泰姆

     The CXSD62104 is equipped with accurate sourcing cur-rent-limit, outputfnq嘉泰姆

under-voltage and output over-voltage protections, being perfect for NB fnq嘉泰姆

applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current. fnq嘉泰姆

A soft-stop function actively discharges the output capaci-tors by the discharge fnq嘉泰姆

device. The CXSD62104 has individual enable controls for PWM channels and fnq嘉泰姆

LDOs. Pulling both ENPWM pin and ENLDO pin low shuts down the whole chipfnq嘉泰姆

with low quiescent current close to zero.fnq嘉泰姆
      The CXSD62104 is available in a TQFN4x4-24A package.fnq嘉泰姆
二.产品特点(Features)fnq嘉泰姆
Wide Input Voltage Range from 6V to 25Vfnq嘉泰姆
Provide 4 Independent Outputs with ±1.5% Accu-fnq嘉泰姆
racy Over-Temperaturefnq嘉泰姆
- PWM1 Controller with Adjustable (2V to 5.5V) Out-putfnq嘉泰姆
PWM2 Controller with Adjustable (2V to 5.5V) Out-putfnq嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V Outputfnq嘉泰姆
100mA Low Dropout Regulator (LDO3) with Fixed 3.3V Outputfnq嘉泰姆
Excellent Line/Load Regulations about ±1.5% Over-Temperature Rangefnq嘉泰姆
±1%, (±1.5%, 50μA) 2.0V Reference Voltage Outputfnq嘉泰姆
Built-In POR Control Scheme Implementedfnq嘉泰姆
Selectable Forced-PWM or Automatic PFM/PWMfnq嘉泰姆
(with Selectable Ultrasonic Operation)fnq嘉泰姆
Constant-On-Time Control Scheme with Frequencyfnq嘉泰姆
Compensation for PWM Modefnq嘉泰姆
Selectable Switching Frequency in PWM Modefnq嘉泰姆
Built-in Digital Soft-Start for PWM Outputs and Soft-fnq嘉泰姆
Stop for PWM Outputs and LDO Outputsfnq嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETfnq嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)fnq嘉泰姆
Built-in Power Good Indicators (PWMs)fnq嘉泰姆
Independent Enable Inputs (PWMs, LDO)fnq嘉泰姆

70% Under-Voltage and 125% Over-Voltage Protec-tions (PWM)fnq嘉泰姆

Adjustable Current-Limit Protection (PWMs)fnq嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)fnq嘉泰姆
Over-Temperature Protectionfnq嘉泰姆
4mmx4mm Thin QFN-24 (TQFN4x4-24A) packagefnq嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)
fnq嘉泰姆

三,应用范围 (Applications)fnq嘉泰姆

Notebook and Sub-Notebook Computersfnq嘉泰姆

Portable Devicesfnq嘉泰姆
DDR1, DDR2, and DDR3 Power Suppliesfnq嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered Devicesfnq嘉泰姆
Graphic Cardsfnq嘉泰姆
Game Consolesfnq嘉泰姆
Telecommunications
fnq嘉泰姆

四.下载产品资料PDF文档 fnq嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持fnq嘉泰姆

 QQ截图20160419174301.jpgfnq嘉泰姆

五,产品封装图 (Package)fnq嘉泰姆


blob.pngblob.pngfnq嘉泰姆

六.电路原理图fnq嘉泰姆


blob.pngfnq嘉泰姆

七,功能概述fnq嘉泰姆


Input Capacitor Selectionfnq嘉泰姆
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selectfnq嘉泰姆
the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMSfnq嘉泰姆
current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors arefnq嘉泰姆
remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-fnq嘉泰姆
side MOSFET with very low-impeadance PCB layout. fnq嘉泰姆
MOSFET Selectionfnq嘉泰姆
The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs shouldfnq嘉泰姆
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:fnq嘉泰姆
· For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFETfnq嘉泰姆
driver will not charge the miller capacitor of this MOSFET.fnq嘉泰姆
In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. Thefnq嘉泰姆
high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driverfnq嘉泰姆
sinking current path. This results in much less switching loss of the low-side MOSFETs. The dutyfnq嘉泰姆
cycle is often very small in high battery voltage applications, and the low-side MOSFET will con-fnq嘉泰姆
duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the powerfnq嘉泰姆
loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFETfnq嘉泰姆
does not have this zero voltage switching condition, and because it conducts for less timefnq嘉泰姆
compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be givenfnq嘉泰姆
to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.fnq嘉泰姆
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitancefnq嘉泰姆
(CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc-fnq嘉泰姆
tion loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given byfnq嘉泰姆
the following equations:fnq嘉泰姆
Layout Considerationfnq嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.fnq嘉泰姆
With power devices switching at higher frequency, the resulting current transient will cause voltage spike acrossfnq嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionfnq嘉泰姆
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,fnq嘉泰姆
current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasiticfnq嘉泰姆
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short andfnq嘉泰姆
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. Andfnq嘉泰姆
signal and power grounds are to be kept separating and finally combined to use the ground plane construction orfnq嘉泰姆

single point grounding. The best tie-point between the signal ground and the power ground is at the negativefnq嘉泰姆
side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are notfnq嘉泰姆
recommended. Below is a checklist for your layout:fnq嘉泰姆
Layout Consideration (Cont.)fnq嘉泰姆
Keep the switching nodes (UGATEx, LGATEx, BOOTx,and PHASEx) away from sensitive small signal nodesfnq嘉泰姆
(REF, ILIMx, and FBx) since these nodes are fast mov-ing signals. Therefore, keep traces to these nodes asfnq嘉泰姆
short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.fnq嘉泰姆

Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce offnq嘉泰姆

CXSD62104fnq嘉泰姆

八,相关产品                 更多同类产品...... fnq嘉泰姆


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Archifnq嘉泰姆

tectufnq嘉泰姆

Phasefnq嘉泰姆

No.offnq嘉泰姆

PWMfnq嘉泰姆

Outputfnq嘉泰姆

Output fnq嘉泰姆

Currentfnq嘉泰姆

(A) fnq嘉泰姆

Inputfnq嘉泰姆

Voltage (V) fnq嘉泰姆

Referencefnq嘉泰姆

Voltagefnq嘉泰姆

(V) fnq嘉泰姆

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maxfnq嘉泰姆

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VM    fnq嘉泰姆

1   fnq嘉泰姆

1     fnq嘉泰姆

30fnq嘉泰姆

2.9    fnq嘉泰姆

13.2fnq嘉泰姆

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12     fnq嘉泰姆

8000fnq嘉泰姆

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