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首页 > Products > Power Management > DC/DC Step-Down Converter > Buck Step-Down Converter >CXSD6273 integrates synchronous buck PWM linear controller, and 0.8V Reference Out Voltage, as well as the monitoring and protection functions into a single package. The fixed 300kHz switchin
CXSD6273 integrates synchronous buck PWM linear controller, and 0.8V Reference Out Voltage, as well as the monitoring and protection functions into a single package. The fixed 300kHz switchin

The CXSD6273 integrates synchronous buck PWM, linear controller, and 0.8V Reference
Out Voltage, as well as the monitoring and protection functions into a single package. The
fixed 300kHz switching frequency synchro-nous PWM controller drives dual N-channel
MOSFETs,which provides one controlled power output with over-voltage and over-current
protections. Linear controller drives an external N-channel MOSFET with under-volt-
age protection.
The CXSD6273 provides excellent regulation for output load variation. An internal 0.8V
temperature-compensated ref-erence voltage is designed to meet the requirement of
low output voltage applications.
The CXSD6273 with excellent protection functions: POR,OCP, OVP and UVP. The
Power-On-Reset (POR) circuit can monitor VCC12 supply voltage exceeds its threshold
voltage while the controller is running, and a built-in digi-tal soft-start provides both outputs
with controlled rising voltage. The Over-Current Protection (OCP) monitors the output current
by using the voltage drop across the lower MOSFET’s RDS(ON), comparing with the voltage
of OCSET pin, VOCSET. The maximum VOCSET voltage is limited to the internal default value
0.25V. In addition, when OCSET pin is floating (no ROCSET resistor), the over current threshold
will also be internal default value, 0.25V. When the output current reaches the trip point, the
controller will shutdown the IC directly, and latch the converter’s output. The Un-der-Voltage Protection (UVP) monitors the voltage of FBL pin for short-circuit protection. When the VFBL is less than
50% of VREF, the controller will shutdown the IC directly.The Over-Voltage Protection (OVP)
monitors the voltage of FB. When the VFB is over 135% of VREF, the controller will
make Low-side gate signal fully turn on until the fault events are removed.

CXSD6273 integrates synchronous buck PWM linear controller, and 0.8V Reference Out Voltage, as well as the monitoring and protection functions into a single package. The   fixed 300kHz switchin
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Product introduction

目录9hI嘉泰姆

1.产品概述                       2.产品特点9hI嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 9hI嘉泰姆
5.产品封装图                     6.电路原理图                   9hI嘉泰姆
7.功能概述                        8.相关产品

一,产品概述(General Description)   9hI嘉泰姆


           The CXSD6273 integrates synchronous buck PWM, linear controller, and 0.8V Reference9hI嘉泰姆
Out Voltage, as well as the monitoring and protection functions into a single package. The  9hI嘉泰姆
fixed 300kHz switching frequency synchro-nous PWM controller drives dual N-channel9hI嘉泰姆
MOSFETs,which provides one controlled power output with over-voltage and over-current9hI嘉泰姆
protections. Linear controller drives an external N-channel MOSFET with under-volt-9hI嘉泰姆
age protection.9hI嘉泰姆
      The CXSD6273 provides excellent regulation for output load variation. An internal 0.8V9hI嘉泰姆
temperature-compensated ref-erence voltage is designed to meet the requirement of9hI嘉泰姆
low output voltage applications.9hI嘉泰姆
      The CXSD6273 with excellent protection functions: POR,OCP, OVP and UVP. The9hI嘉泰姆
Power-On-Reset (POR) circuit can monitor VCC12 supply voltage exceeds its threshold9hI嘉泰姆
voltage while the controller is running, and a built-in digi-tal soft-start provides both outputs9hI嘉泰姆
with controlled rising voltage. The Over-Current Protection (OCP) monitors the output current9hI嘉泰姆
by using the voltage drop across the lower MOSFET’s RDS(ON), comparing with the voltage9hI嘉泰姆
of OCSET pin, VOCSET. The maximum VOCSET voltage is limited to the internal default value9hI嘉泰姆
0.25V. In addition, when OCSET pin is floating (no ROCSET resistor), the over current threshold9hI嘉泰姆
will also be internal default value, 0.25V. When the output current reaches the trip point, the9hI嘉泰姆
controller will shutdown the IC directly, and latch the converter’s output. The Un-der-Voltage Protection (UVP) monitors the voltage of FBL pin for short-circuit protection. When the VFBL is less than9hI嘉泰姆
50% of VREF, the controller will shutdown the IC directly.The Over-Voltage Protection (OVP)9hI嘉泰姆
monitors the voltage of FB. When the VFB is over 135% of VREF, the controller will9hI嘉泰姆
make Low-side gate signal fully turn on until the fault events are removed.9hI嘉泰姆
二.产品特点(Features)9hI嘉泰姆


1.)Two Regulated Voltages and REF_OUT    Synchronous Buck Converter9hI嘉泰姆
     Linear Regulator9hI嘉泰姆
    REF_OUT = 0.8V±1% with 3mA Source Current9hI嘉泰姆
2.)Single 12V Power Supply Required9hI嘉泰姆
3.)Excellent Both Output Voltage Regulation9hI嘉泰姆
    0.8V Internal Reference9hI嘉泰姆
    ±1% Over Line Voltage and Temperature9hI嘉泰姆
4.)Integrated Soft-Start for PWM and Linear Outputs9hI嘉泰姆
5.)300KHz Fixed Switching Frequency9hI嘉泰姆
6.)Voltage Mode PWM Control Design and Up to 89%(Typ.) Duty Cycle9hI嘉泰姆
7.)Under-Voltage Protection Monitoring Linear Out-put9hI嘉泰姆
8.)Over-Voltage Protection Monitoring PWM Output9hI嘉泰姆
9.)Over-Current Protection for PWM Output  Sense Low-side MOSFET’s RDS(ON)9hI嘉泰姆

10.)SOP-14, SSOP-16 and Compact QFN4x4-16 pack-ages9hI嘉泰姆
11.)Lead Free and Green Devices Available(RoHS Compliant)9hI嘉泰姆
三,应用范围 (Applications)9hI嘉泰姆


      Graphic Cards9hI嘉泰姆
四.下载产品资料PDF文档 9hI嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持9hI嘉泰姆

 QQ截图20160419174301.jpg9hI嘉泰姆

五,产品封装图 (Package)9hI嘉泰姆
9hI嘉泰姆
FUNCTION NAMEFUNCTION9hI嘉泰姆

PIN NO.9hI嘉泰姆

NAME9hI嘉泰姆

FUNCTION9hI嘉泰姆

SOP-149hI嘉泰姆

SSOP-169hI嘉泰姆

QFN4x4-169hI嘉泰姆

   

19hI嘉泰姆

159hI嘉泰姆

 

BOOT9hI嘉泰姆

This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internaldiode, and the power supply voltage VCC12, generates the bootstrap voltage9hI嘉泰姆
for the upper gate diver (UGATE).9hI嘉泰姆

29hI嘉泰姆

29hI嘉泰姆

169hI嘉泰姆

FS_DIS9hI嘉泰姆

This pin provides shutdown function. When pulling low the FS_DIS pin near GND will shutdown both regulators; almost any NFET or other pull-down device (< 1k. impedance) should work. Upon release of the FS_DIS pin, it will9hI嘉泰姆
enable both outputs back into regulation.9hI嘉泰姆

39hI嘉泰姆

39hI嘉泰姆

19hI嘉泰姆

COMP9hI嘉泰姆

This pin is the output of PWM error amplifier. It is used to set the compensation components.9hI嘉泰姆

49hI嘉泰姆

49hI嘉泰姆

29hI嘉泰姆

FB9hI嘉泰姆

This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored9hI嘉泰姆
for under-voltage protection, when the FB voltage is under 50% of reference9hI嘉泰姆
voltage (0.4V), both outputs will be shutdowned immediately.9hI嘉泰姆

59hI嘉泰姆

59hI嘉泰姆

39hI嘉泰姆

DRIVE9hI嘉泰姆

This pin drives the gate of an external N-channel MOSFET for linear regulator.9hI嘉泰姆
It is also used to set the compensation for some specific applications, for9hI嘉泰姆
example, with low values of output capacitance and ESR.9hI嘉泰姆

69hI嘉泰姆

69hI嘉泰姆

49hI嘉泰姆

FBL9hI嘉泰姆

This pin is the inverting input of the linear regulator error amplifier. It is used to9hI嘉泰姆
set the output voltage. This pin is also monitored for under-voltage protection,when the FBL voltage is under 50% of reference voltage(0.4V), both outputs will be shutdown immediately.9hI嘉泰姆

79hI嘉泰姆

7,89hI嘉泰姆

5,69hI嘉泰姆

GND9hI嘉泰姆

This pin is the signal ground pin. Connect the GND pin to a good ground plane.9hI嘉泰姆

89hI嘉泰姆

9,109hI嘉泰姆

7,89hI嘉泰姆

VCC129hI嘉泰姆

Power supply input pin. Connect a nominal 12V power supply to this pin. Thepower- on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10μF) be connected to GND for noise decoupling.9hI嘉泰姆

99hI嘉泰姆

119hI嘉泰姆

99hI嘉泰姆

REF_OUT9hI嘉泰姆

This pin provides a buffed voltage, which is from internal reference voltage. It is recommended that a 1mF capacitor is connected to ground for stability.9hI嘉泰姆
When VOCSET is above 1V, the REF_OUT buffer will be closed, the VREF_OUT is 0V.9hI嘉泰姆

109hI嘉泰姆

129hI嘉泰姆

109hI嘉泰姆

OCSET9hI嘉泰姆

Connect a resistor (ROCSET) from this pin to GND, an internal 40mA current source will flow through this resistor and create a voltage drop. When VCC12 reaches the POR rising threshold voltage, the voltage drop of ROCSET will be9hI嘉泰姆
memoried and compared with the voltage across the lower MOSFET. The threshold of the over current limit is therefore given by: IOCSET × ROCSET ILIMIT = RDS(ON)(LOW − Side)9hI嘉泰姆
The CXSD6273 has a internal OCP voltage source, and the value is around 0.25V. When the ROCSET x IOCSET is bigger than 0.25V or the OCSET PIN is floating (no ROCSET resistor), the over current threshold will be the internal default value 0.25V.9hI嘉泰姆

119hI嘉泰姆

139hI嘉泰姆

119hI嘉泰姆

LGATE9hI嘉泰姆

This pin is the gate driver for the lower MOSFET of PWM output.9hI嘉泰姆

129hI嘉泰姆

149hI嘉泰姆

129hI嘉泰姆

PGND9hI嘉泰姆

This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board.9hI嘉泰姆

139hI嘉泰姆

159hI嘉泰姆

139hI嘉泰姆

PHASE9hI嘉泰姆

This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source, and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the lower9hI嘉泰姆
MOSFET for over-current protection.9hI嘉泰姆

149hI嘉泰姆

169hI嘉泰姆

149hI嘉泰姆

UGATE9hI嘉泰姆

This pin is the gate driver for the upper MOSFET of PWM output.9hI嘉泰姆

六.电路原理图9hI嘉泰姆


blob.png9hI嘉泰姆

七,功能概述9hI嘉泰姆


Function Description (Cont.)9hI嘉泰姆

Over-Current Protection (Cont.)9hI嘉泰姆
When OCSET PIN is floating, the VOCSET will be pulled high and the over current threshold will be the9hI嘉泰姆

 internal default value 0.25V. When the voltage drop across the lower MOSFET’s RDS(ON) is larger than9hI嘉泰姆

 0.25V, an over-cur-rent condition is detected, the controller will shutdown the IC directly, and latch 9hI嘉泰姆

the converter’s output. 9hI嘉泰姆
Over Voltage Protection9hI嘉泰姆
The FB pin is monitored during converter operation by its own Over Voltage(OV) comparator. If the9hI嘉泰姆

 FB voltage is over 135% of the reference voltage, the controller will make Low-Side gate signal fully 9hI嘉泰姆

turn on until the fault events are removed.9hI嘉泰姆
Under Voltage Protection9hI嘉泰姆
The FBL pin is monitored during converter operation by its own Under Voltage (UV) comparator. If 9hI嘉泰姆

the FBL voltage drop below 50% of the reference voltage (50% of 0.8V =0.4V), a fault signal is 9hI嘉泰姆

internally generated, and the de-vice turns off both high-side and low-side MOSFET and the 9hI嘉泰姆

converter’s output is latched to be floating. The con-troller will shutdown the IC directly.9hI嘉泰姆
Shutdown and Enable9hI嘉泰姆
Pulling low the FS_DIS pin near GND by an open drain transistor or other pull-down device 9hI嘉泰姆

(<1k. impedance)will shutdown both regulators. Upon release of the FS_DIS pin, it will9hI嘉泰姆

 enable both outputs back into regulation. In shutdown mode, the UGATE and LGATE9hI嘉泰姆

 turn off and pull to PHASE and GND respectively.9hI嘉泰姆

八,相关产品                          更多同类产品...... 9hI嘉泰姆


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