The CXMC33129 is an 8-bit RISC-based microcontroller with a wide operating voltage range of 2.5V to 3.6V for battery-powered and low-power applications. The chip has built-in high-speed (4.9MHz) and low-speed (32kHz)RC oscillators, supporting a variety of operating modes, including normal mode, sleep mode, idle mode 0 and idle mode 1, which can significantly reduce system power consumption.
Its program memory is 8K × 16-bit OTP, data memory is 256 bytes SRAM, supports 61 instructions, all instructions can be completed in 1 or 2 cycles, high execution efficiency
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[ CXMC33129 ]"
CXMC33129: A high-performance low-power 8-bit RISC microcontroller
In today's era of vigorous development of the Internet of Things and smart devices, microcontroller (MCU) as the core control unit, its performance, power consumption and integration have become the key factors for developers to select. CXMC33129 is an 8-bit RISC architecture microcontroller born in this context. With its low power consumption, high integration and rich peripheral resources, it is widely used in smart sensors, portable devices, industrial control and other fields.
1. Chip Overview and Core Features
The CXMC33129 is an 8-bit RISC-based microcontroller with a wide operating voltage range of 2.5V to 3.6V for battery-powered and low-power applications. The chip has built-in high-speed (4.9MHz) and low-speed (32kHz)RC oscillators, supporting a variety of operating modes, including normal mode, sleep mode, idle mode 0 and idle mode 1, which can significantly reduce system power consumption.
The program memory is 8K × 16-bit OTP, the data memory is 256 bytes SRAM, and it supports 61 instructions. All instructions can be completed in 1 or 2 cycles, and the execution efficiency is high. In addition, the chip integrates a variety of peripheral modules, including:
◆1-Channel 8-Bit Successive Approximation ADC
◆2-channel 24-bit & Sigma;-& Delta; high-precision ADC
◆Built-in temperature sensor
◆2 8-bit PWM outputs
◆10/13 programmable I/O ports
◆5 interrupt sources, support multiple wake-up modes
1.2. The package provides SOP16 and SOP 1000.00g options to facilitate hardware design in different scenarios..
2. Core Architecture and Memory Organization
The CXMC33129 adopts the classic Harvard architecture, the program memory and data memory are separated, and the simultaneous access is supported, which improves the efficiency of instruction execution. The program memory address space is 8K × 16 bits, of which 0000H is the reset vector address, 0004H ~ 0018H is the interrupt vector area, and the user code can be stored from 0000H.
The data memory is divided into special function registers (SFR) and general purpose registers (GPR), and the address range is 000H ~ 1FFH. The SFR is used to control peripheral and system states, and the GPR is used for data storage and computing intermediate results. The indirect addressing register INDF0/INDF1 is used in conjunction with the pointer register INDP0/INDP1 to support flexible data access.
2.1. Core architecture
2.2. Memory structure.
The microcontroller consists of two memory modules: program memory and data memory. Each module has its own total
line, two memory modules can be accessed simultaneously in the same cycle.
2.2.1 Program memory
The program memory is used to store the user code, that is, the storage program. The microcontroller has a 13-bit wide program counter, the maximum
Addressable 8K x 16 program storage space. The microcontroller has 8K x 16 program memory.
Some addresses in program memory are reserved for special purposes such as resets and interrupts. 0000H is reserved for use as a microcontroller complex.
Bit after the program start address. When the chip is initialized or reset occurs, the program will jump to this address and begin execution.
0004H ~ 0018H are interrupt vectors used to execute interrupt service routines. 1 DFFFH ~ 1FFFH is the encryption area is not available.
2.2.2 Data storage
2.2.2.1) Data memory structure.
The data memory consists of special function registers (SFRs) and general purpose registers (GPRs). operation of the SFR control device,
These registers have specific addresses and are closely related to the correct operation of the microcontroller. Most special function registers are available in the program.
Read and write directly under sequential control, while some are protected from users. GPR is data storage and rewriting
All addresses can be read and written under program control.
The starting address of the data memory of the microcontroller is "000H", and the address range is 000H ~ 1FFH.
2.2.2.2) Special Function Register Description
Most of the special function registers are described in detail in the related functions, but several registers are described separately in this section.
indirect addressing register-INDF0,INDF1
The addresses of the indirect addressing registers INDF0 and INDF1 are located in the data storage area, but they do not have actual physical addresses.
Indirect addressing is the use of indirect addressing registers and indirect addressing pointers to operate on data instead of defining actual memory.
Direct memory addressing method for memory addresses. Any action on the indirect addressed registers (INDF0 and INDF1),
Corresponding read/write operations are generated for the memory addresses specified by the indirect addressing pointers (INDP0 and INDP1). They always
In pairs, INDF0 and INDP0 can access Bank 0, while INDF1 and INDP1 can access all Bank
(This microcontroller only Bank0).
Indirect Addressing Pointer-INDP0,INDP1
This series of microcontrollers provides two indirect addressing pointers, INDP0 and INDP1. Since these pointers are in the data memory.
It can be operated like an ordinary register, thus providing an efficient method of addressing and data tracing. When looking for indirect
When the address register performs any operation, the actual address pointed to by the microcontroller is the address specified by the indirect addressing pointer.
INDP0 and INDF0 are used to access Bank 0, while INDP1 and INDF1 can access all
Bank. Indirect addressing only accesses general registers, I .e., the most significant bit of a 9-bit address defaults to high.
Status Register-STATUS
The 8-bit register includes zero flag bit (Z), carry flag bit (C), auxiliary carry flag bit (AC), overflow flag bit (OV),
Pause flag bit (PDF), and watchdog overflow flag bit (TO). These flag bits simultaneously record the state data and calculation of the microcontroller.
surgery/logic operations.
C: When the result of the addition operation produces a carry, or the result of the subtraction operation does not produce a borrow, then C is set, otherwise
C is cleared, and C is also affected by the shift instruction with carry.
AC: When the result of the low nibble addition operation produces a carry, or the result of the low nibble subtraction operation does not produce a borrow,
AC is set, otherwise AC is cleared.
Z: Z is set when the result of the arithmetic or logical operation is zero, otherwise Z is cleared.
OV: OV is set when the carry state XOR result of the upper two bits of the operation result is 1, otherwise OV is cleared.
PDF: System power-up or execution of the "CLRWDT" command will clear the PDF, while execution of the "STOP" command will set the PDF.
TO: TO will be cleared when the system is powered on or "CLRWDT" or "STOP" instructions are executed, and will be set when WDT overflows.
That.
In addition, the status register will not be automatically pushed into the stack when entering an interrupt program or executing a subroutine call.
Save. If the contents of the status register are important and the interrupt subroutine changes the contents of the status register, you need to save
Back up for recovery.
Bit 7~6 is not used, read as "0"
Bit 5 TO: Watchdog Overflow Flag Bit
0: System power up or execute "CLRWDT" or "STOP" command
1:WDT overflow
Bit 4 PDF: Pause Flag Bit
0: System power up or execute "CLRWDT" command
1: Executing the "STOP" instruction will set the PDF bit.
Bit 3 OV: overflow flag bit
0: when no overflow occurs
1: When the XOR result of the carry state of the upper two digits of the operation result is 1
Bit 2 Z: zero flag bit
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1 AC: auxiliary carry flag bit
0: when there is no auxiliary carry
1: When the addition of the low byte causes a carry or subtraction does not cause a borrow
Bit 0 C: carry flag bit (opposite polarity when borrowing)
0: when there is no carry
1: When addition causes carry or subtraction does not cause borrowing, the shift instruction will also affect the C flag bit C.
It is also affected by the cyclic shift instruction.
3. System Clock and Power Management
CXMC33129 built-in two RC oscillators: high-speed HIRC(4.9MHz) and low-speed LIRC(32kHz). Users can select the system clock source and its frequency division ratio through the SMOD register, and support four frequencies of fH, fH/2, fH/4, and fH/8, taking into account performance and power consumption.
The chip supports four modes of operation:
◆Normal mode: All modules run with the highest power consumption and the strongest performance.
◆Sleep mode: The CPU and system clock are turned off, only the low-speed oscillator and WDT run, with the lowest power consumption.
◆Idle Mode 0The CPU stops, the system clock is turned off, and some peripherals (such as Timer0) can still run.
◆Idle Mode 1The CPU stops, the system clock continues to run, and peripheral functions are maintained.
Through the STOP instruction combined with the IDLEC and FSYSEN bits in the SMOD register, the working mode can be flexibly switched to achieve fine control of power consumption.
3.1. Oscillator
The microcontroller has two internal fully integrated oscillator, high-speed oscillator for the internal 4.9MHzRC oscillator, low-speed oscillation
The oscillator is an internal 32kHz RC oscillator.
Internal high-speed RC oscillator-HIRC
The internal high-speed RC oscillator is a fully integrated system oscillator that requires no other external devices. Chips are made at the time of manufacture
Adjusted and internal frequency compensation circuit, so that the oscillation frequency due to VDD, temperature and chip manufacturing process of different effects.
Minimize
Internal low speed RC oscillator-LIRC
The internal 32kHz system oscillator is a low speed oscillator. LIRC is a fully integrated RC oscillator, no external devices,
At room temperature of 3.3V, the oscillation frequency value is 32kHz. The chip is adjusted during manufacture and contains frequency compensation electricity internally.
The oscillation frequency is minimized due to VDD, temperature, and different chip fabrication processes. Power on the system,
The LIRC oscillator is enabled, and there is no register bit to divide the oscillator.
System Clock Configuration
3.3. Related special function registers.
The SMOD register is used to control the internal clock of the microcontroller.
Bit 7~4 is not used, read as "0"
Bit 3~2 CP1 ~ CP0: System clock select bit, used to select the system clock source.
00：fH
01：fH/2
10：fH/4
11：fH/8
Bit 1 IDLEC: Idle Mode Control Bit
0: Remove energy (enter sleep mode after STOP instruction is executed)
1: enable
This bit is an idle mode control bit that determines the action that occurs after the STOP instruction is executed. If this bit is high, when the command
After STOP is executed, the microcontroller enters idle mode. Whether to enter idle mode 0 or idle mode 1 depends on
FSYSEN bit, if the FSYSEN bit is high, the CPU stops running in idle mode 1, the system clock will continue to work
to keep peripheral functions working; if FSYSEN is low, both CPU and system clocks will stop in idle mode 0
Run. If this bit is low, the microcontroller will enter sleep mode after the STOP instruction is executed.
Bit 0 FSYSEN: fSYS control bit in IDLE mode
0: divide energy
1: enable
3.4. System working mode
This series of single-chip microcomputer has four different working modes, each has its own characteristics, according to the application of different performance and
Different operating modes can be selected for power consumption requirements. SCM normal work has normal mode. The remaining 3 working modes: Hugh
Sleep Mode, Idle Mode 0 and Idle Mode 1 are used to save power when the MCU CPU is turned off.
Normal mode
As the name implies, this is the main mode of operation, all the functions of the microcontroller can be implemented in this mode and the system clock is controlled
A high speed oscillator is provided. In this mode, the clock source for the normal operation of the microcontroller comes from the HIRC oscillator. High Speed Oscillator Frequency
The rates can be divided into unequal ratios of 1 to 8, the actual ratio being selected by CP1 to CP0 in the SMOD register. single chip microcomputer
Using high-speed oscillator frequency division as the system clock can reduce the operating current.
Sleep mode
After the STOP instruction is executed and the IDLEC bit in the SMOD register is low, the system enters sleep mode. In the dormant mode
where the CPU stops running. Watchdog timer function enabled, fLContinue to run.
Idle Mode 0
When the STOP instruction is executed and the IDLEC bit in the SMOD register is high and the FSYSEN bit in the SMOD register is low,
The system enters idle mode 0. In idle mode 0, the system clock stops and the CPU stops working, but some peripheral functions
Such as watchdog timer and timer/counter will continue to work.
Idle Mode 1
After the STOP instruction is executed and the IDLEC bit in the SMOD register is high and the FSYSEN bit in the SMOD register is high,
The system goes into idle mode 1. In idle mode 1, the CPU stops, but provides a clock source to some peripheral functions
Such as watchdog timer and timer/counter. In idle mode 1, the system clock continues to run.
The power-saving working mode of the MCU core is mainly realized by turning off the clock of the relevant part;
PWM, 8bit ADC clock is the system clock
After the system enters sleep or idle mode, you can wake up in the following ways:
● System interruption
● WDT overflow
Watchdog timer reset occurs if awakened by WDT overflow. This wake-up method will reset the system and can
Its wake-up source is determined by the TO and PDF bits in the status register. The system is powered up or the command to clear the watchdog is executed,
The PDF is cleared; the STOP instruction is executed and the PDF is set. Watchdog counter overflow will set the TO flag and call
This reset resets the program counter and stack pointer, while the other flags remain in their original state.
If the system is awakened by an interrupt, there are two possibilities. The first case is: the relevant interrupt can be removed or the interrupt makes.
Yes and the stack is full, the program continues after the "STOP" instruction. In this case, the interrupt that wakes up the system will
Wait until the relevant interrupt is enabled or the stack layer is available before execution. The second case is: the relevant interrupt is enabled and the stack
is not full, the interrupt can be executed immediately. If the interrupt flag bit has been set
"1", the wake-up function of the relevant interrupt will be invalid.
4. peripheral resources
1. Timer counter Timer0 and Timer1
Timer0 is an 8-bit programmable timer that supports the system clock or low-speed clock as the source, the pre-frequency ratio is adjustable, and the interrupt can be triggered when it overflows. Timer1 is a fixed cycle counter, dedicated to generating time-based interrupts, suitable for application scenarios that require periodic wake-up.
2. PWM module
The chip provides two 8-bit PWM outputs. The duty cycle can be set through PWM0 and PWM1 registers. PWMCT registers control output enable and polarity reversal. It is suitable for motor control, LED dimming and other applications.
3. ADC Module
◆8-bit SAR ADC: The conversion period is 32 machine cycles, suitable for general precision analog signal acquisition.
◆24位Σ-Δ ADC: Support differential input, adjustable gain (2 or 128 times), optional output rate (10/20/40/80Hz), suitable for high-precision measurement such as weighing, temperature, pressure, etc.
4. Temperature sensor
The internal temperature sensor data can be read through channel 2 of the 24-bit ADC. The output value is linearly related to the temperature. The typical value is the output 224700 at 25 ℃ (after shifting 2 bits to the right). The output increases by 740 for each 1 ℃ increase, which is suitable for ambient temperature monitoring.
5. Interrupt the system
The chip supports 5 interrupt sources, in descending order of priority: external interrupt, Timer0 interrupt, Timer1 interrupt, 24-bit ADC interrupt, 8-bit ADC interrupt. Each interrupt has an independent enable bit and flag bit, supporting edge trigger and wake-up functions.
5. Instruction Set and Programming Model
The CXMC33129 provides 61 instructions, covering arithmetic operations, logical operations, data transfer, bit operations, jumps, and other functions. All instructions can be completed in 1 or 2 cycles, support direct, indirect and immediate addressing mode, programming flexible and efficient.
Particularly worth mentioning is its BCD adjustment instruction (BTD), which can be used for decimal operations, suitable for digital tube display, metering equipment and other scenarios.
5.1. Instruction description convention
m data register address
R m corresponds to data memory
ACC accumulator (working register)
B The bit address in the eight-bit data register.
K immediately.
5.2. List of Directives
5.3. Directive definition conventions
k: Immediate number
m: data memory address
ACC: Accumulator
B: bit 0~7
1. arithmetic operation
1、ADDAM m,1
The instruction description adds the specified data memory and accumulator content, and the result is stored in the accumulator.
Function representation ACC & larr; m ACC
Impact flags OV, Z, AC, C
2、ADDAM m,0
The instruction description adds the contents of the specified data memory and accumulator, and the result is stored in the specified data memory.
Function Representation m & larr; m ACC
Impact flags OV, Z, AC, C
3、ADDAL k
The instruction description adds the accumulator to the immediate number and stores the result in the accumulator.
Function Representation ACC & larr; k ACC
Impact flags OV, Z, AC, C
4、ADDAMC m,1
The instruction description adds the specified data memory, the contents of the accumulator, and the carry flag, and the result is stored in the accumulator.
Function representation ACC & larr; m ACC C
Impact flags OV, Z, AC, C
5、ADDAMC m,0
The instruction description adds the specified data memory, accumulator content, and the forward flag bit, and the result is stored in the specified data.
Memory.
Function Representation m & larr; m ACC C
Impact flags OV, Z, AC, C
6、SUBAL k
The instruction description subtractions the contents of the immediate number de-accumulator and stores the result in the accumulator. If the result is negative, the C flag is cleared
is 0, otherwise the result is positive or 0, and the C flag bit is set to 1.
Function Representation ACC & larr; k-ACC
Impact flags OV, Z, AC, C
7、SUBAM m,1
The instruction description subtracts the contents of the accumulator from the data in the specified data memory and stores the result in the accumulator. If the result is
Negative, the C flag bit is cleared to 0, otherwise the result is positive or 0, and the C flag bit is set to 1.
Function Representation ACC & larr; m-ACC
Impact flags OV, Z, AC, C
8、SUBAM m,0
The instruction description subtracts the contents of the accumulator from the data in the specified data memory and stores the result in the specified data memory. Such
If the result is negative, the C flag bit is cleared to 0, otherwise the result is positive or 0, and the C flag bit is set to 1.
Function Representation m & larr; m-ACC
Impact flags OV, Z, AC, C
9、SUBAMC m,1
The instruction description subtracts the contents of the accumulator from the specified data memory minus the reverse of the carry flag, and the result is stored in the tired.
The additive. If the result is negative, the C flag bit is cleared to 0, otherwise the result is positive or 0, and the C flag bit is set to 1.
Function Representation ACC & larr; m-ACC- (!C)
10、SUBAMC m,0
The instruction description subtracts the contents of the accumulator from the specified data memory minus the reverse of the carry flag, and the result is stored in the number.
According to the memory. If the result is negative, the C flag bit is cleared to 0, otherwise the result is positive or 0, and the C flag bit is set to 1.
functional representation m & larr; m-ACC- (!C)
Impact flags OV, Z, AC, C
11、BTD m
The instruction description is generally used together with addition, and the function is to directly treat the addend and the addend in the last addition as decimal
The system is operated on and the decimal sum is stored in m. If the value of the lower four bits is greater than "9" or AC = 1, then the BCD tone
The integer is executed to add "6" to the original value, otherwise the original value remains unchanged; If the value of the top four bits is greater than "9" or C = 1, then
The BCD adjustment is performed by adding "6" to the original value ". The BCD conversion is essentially performed based on the accumulator and flag bits.
The addition operation of 00H,06H,60H or 66H is stored in the data memory. Only carry flag bit C is affected,
Used to indicate whether the sum of the original BCDs is greater than 100, and can be added to double-precision decimal numbers.
Function indicates m & larr; ACC 00H or
m ← ACC 06H 或
m ← ACC 60H 或
M ← ACC 66H
Impact flag C
For example, in the last addition,
29H 35H=5EH
directly seen
29D 35D=64D → m
2. logic operation
1、ANDAM m,1
The instruction description will specify the contents of the data memory and the data in the accumulator to do a logical and, the results are stored in the accumulator.
Function indicates ACC & larr; m "AND" ACC
Impact flag Z
2、ANDAM m,0
The instruction description will specify the contents of the data memory and the data in the accumulator to do a logical and, the results are stored in the data memory.
Functional representation m & larr; m "AND" ACC
Impact flag Z
3、ANDAL k
Instruction Description The data in the accumulator and the immediate number are logically and the results are stored in the accumulator.
Function Representation ACC & larr; k "AND" ACC
Impact flag Z
4、ORAM m,1
The instruction description stores the data in the specified data memory and the accumulator logic or, and the result is stored in the accumulator.
Function means ACC & larr; m "OR" ACC
Impact flag Z
5、ORAM m,0
The instruction description places the data in the specified data memory and the accumulator logic or, and the result is placed in the data memory.
Function Representation m & larr; m "OR" ACC
Impact flag Z
6、ORAL k
The instruction description stores the data in the accumulator and the immediate logical or, and the result is stored in the accumulator.
Function Representation ACC & larr; k "OR" ACC
Impact flag Z
7、XORAM m,1
The instruction description stores the specified data memory content and the data logic of the accumulator, and the result is stored in the accumulator.
Functional representation ACC & larr; m "XOR" ACC
Impact flag Z
8、XORAM m,0
The instruction description will specify the contents of the data memory and the data logic of the accumulator, and the result will be placed in the data memory.
Functional representation m & larr; m "XOR" ACC
Impact flag Z
9、XORAL k
The instruction description stores the data of the accumulator with the immediate logical difference or, and the result is stored in the accumulator.
Function Representation ACC & larr; k "XOR" ACC
Impact flag Z
10、CPL m,0
The instruction description will specify that each bit in the data memory is logically inverted, equivalent to changing from 1 to 0 or 0 to 1.
Function representation m & larr; ~ m
Impact flag Z
11、CPL m,1
The instruction description will specify that each bit in the data memory is logically inverted, equivalent to changing from 1 to 0 or 0 to 1, and the result is stored.
The accumulator is stored back and the contents of the data memory remain unchanged.
Functional representation ACC & larr; ~ m
Impact flag Z
3. Increment and Decrease
1、INC m,0
指令说明 将指定数据存储器的内容加1。
Function representation m & larr; m 1
Impact flag Z
2、INC m,1
The instruction description adds 1 to the contents of the specified data memory, stores the result back to the accumulator and maintains the contents of the specified data memory.
No change.
Function representation ACC & larr; m 1
Impact flag Z
3、DEC m,0
The instruction description subtracts 1 from the specified data memory contents.
Function representation m & larr; m - 1
Impact flag Z
4、DEC m,1
The instruction description reduces the contents of the specified data memory by 1, stores the result back to the accumulator and keeps the specified data memory.
No change.
Function Representation ACC & larr; m - 1
Impact flag Z
4. shift
1、RR m,0
The instruction description circularly shifts the contents of the specified data memory by 1 bit to the right and bit 0 to bit 7.
Function representation m. B & larr; m.(B 1) (B = 0~6)
m.7 ← m.0
Impact Flag None
2、RR m,1
The instruction description shifts the contents of the specified data memory to the right by 1 bit, the 0th to the 7th bit, and stores the shift result to the tired
The contents of the specified data store remain unchanged.
Function representation ACC. B & larr; m.(B 1) (B = 0~6)
ACC.7 ← m.0
Impact Flag None
3、RRC m,0
The instruction description shifts the contents of the specified data memory together with the carry flag to the right by 1 bit, and the 0th bit replaces the carry flag and the original.
The carry flag is moved to the 7th position.
Function representation m. B & larr; m.(B 1) (B = 0~6)
m.7 ← C
C ← m.0
Impact flag C
4、RRC m,1
The instruction description shifts the contents of the specified data memory together with the carry flag to the right by 1 bit, and the 0th bit replaces the carry flag and the original.
The carry flag is moved to the 7th bit, and the shift result is sent back to the accumulator, but the contents of the specified data register remain unchanged.
Function representation ACC. B & larr; m.(B 1) (B = 0~6)
ACC.7 ← C
C ← m.0
Impact flag C
5 、 RL m,0
The instruction specification shifts the contents of the specified data memory left by 1 bit, and the 7th to the 0th bit.
Function representation m.(B 1) & larr; m. B (B = 0~6)
m.0 ← m.7
Impact Flag None
6 、 RL m,1
The instruction description shifts the contents of the specified data memory left by 1 bit, and the 7th bit is shifted to the 0th bit, and the result is sent to the accumulator, and.
The contents of the specified data holder remain unchanged.
Function representation ACC.(B 1) & larr; m. B (B = 0~6)
ACC.0 ← m.7
Impact Flag None
7、RLC m,0
The instruction description shifts the contents of the specified data memory, together with the carry flag, to the left by 1 bit, with the 7th bit replacing the carry flag and the original
The carry flag is moved to the 0th bit.
Function representation m.(B 1) & larr; m. B (B = 0~6)
m.0 ← C
C ← m.7
Impact flag C
8、RLC m,1
The instruction description shifts the contents of the specified data memory, together with the carry flag, to the left by 1 bit, with the 7th bit replacing the carry flag and the original
The carry flag is moved to bit 0, and the shift result is sent back to the accumulator, but the contents of the specified data register remain unchanged.
Function representation ACC.(B 1) & larr; m. B (B = 0~6)
ACC.0 ← C
C ← m.7
Impact flag C
5. data transfer
1 、 MOVMA m
The instruction description copies the contents of the specified data memory to the accumulator.
Function Representation ACC & larr; m
Impact Flag None
2
The instruction description loads an 8-bit immediate into the accumulator.
Function Representation ACC & larr; k
Impact Flag None
3 its MOVAM m
The instruction description copies the contents of the accumulator to the specified data memory.
Function Representation m & larr; ACC
Impact Flag None
6. bit operation
1、CLRB m,b
The instruction description cleats the B- bit contents of the specified data memory.
Function representation m, B & larr; 0
Impact Flag None
2、SETB m,b
The instruction description will specify that the B- th position of the data memory is 1.
Function representation m, B & larr; 1
Impact Flag None
7. conditional transfer
1 、 SZ m,0
The instruction description determines whether the content of the specified data memory is 0, and if it is 0, the program skips the next instruction execution. By
An empty instruction cycle is required to be inserted when the next instruction is obtained, so this instruction is a 2-cycle instruction. If the knot
If it is not 0, the program continues to the next instruction.
function means that if m = 0, skip the next instruction execution
Impact Flag None
2 、 SZ m,1
The instruction description copies the contents of the specified data memory to the accumulator and determines whether the contents of the specified data memory are 0,
If 0 skips the next instruction. This refers to the fact that an empty instruction cycle is required to be inserted when the next instruction is fetched.
command for 2 cycles. If the result is not 0, the program continues with the next instruction.
Function means ACC & larr; m, if m = 0, skip the next instruction execution
Impact Flag None
3 、 SZB m,b
The instruction description determines whether the B- th bit of the specified data memory is 0, and if it is 0, skips the next instruction. Due to acquisition
The next instruction will require an empty instruction cycle to be inserted, so this instruction is a 2-cycle instruction. If the result is not
0, the program continues with the next instruction.
Function means that if m, B = 0, skip the next instruction execution
Impact Flag None
4 、 FZBN m,b
The instruction description determines the I-th bit of the specified data memory, and if it is not 0, the program skips the next instruction execution. Due to take
The next instruction will require the insertion of an empty instruction cycle, so this instruction is a 2-cycle instruction. If the result is
0, the program continues with the next instruction.
Function means that if m. I & ne;0, skip the next instruction execution
Impact Flag None
The instruction description determines whether the B- th bit of the specified data memory is 0, and if it is 0, skips the next instruction. Due to acquisition
The next instruction will require an empty instruction cycle to be inserted, so this instruction is a 2-cycle instruction. If the result is not
0, the program continues with the next instruction.
Function means that if m, B = 0, skip the next instruction execution
Impact Flag None
5 、 CHINC m,0
The instruction description adds 1 to the contents of the specified data memory, determines whether it is 0, and skips the next instruction if it is 0. By
An empty instruction cycle is required to be inserted when the next instruction is obtained, so this instruction is a 2-cycle instruction. If the knot
If it is not 0, the program continues to the next instruction.
The function represents m & larr; m 1, if m = 0 skips the next instruction execution
Impact Flag None
6 、 SZDEC m,0
The instruction description subtracts the contents of the specified data memory by 1, determines whether it is 0, and skips the next instruction if it is 0,
An empty instruction cycle is required to be inserted when the next instruction is obtained, so this instruction is a 2-cycle instruction. If the knot
If it is not 0, the program continues to the next instruction.
function indicates m & larr; m -1, if m = 0 skips the next instruction execution
Impact Flag None
7 、 CHINC m,1
The instruction description adds 1 to the contents of the specified data memory, determines whether it is 0, and skips the next instruction if it is 0.
The result is stored in the accumulator, but the contents of the specified data store remain unchanged. Because the next instruction will be required.
Insert an empty instruction cycle, so this instruction is a 2-cycle instruction. If the result is not 0, the program continues
the next instruction.
Function indicates ACC & larr; m 1, if ACC = 0 skips the next instruction execution
Impact Flag None
8 、 SZDEC m,1
The instruction description subtracts the contents of the specified data memory by 1, determines whether it is 0, and skips the next instruction if it is 0.
The results will be stored in the accumulator, but the contents of the specified data memory will remain unchanged. Since the next instruction will be required to insert a
Empty instruction cycle, so this instruction is a 2-cycle instruction. If the result is not 0, the program continues to the next finger.
Order.
function indicates ACC & larr; m-1, if ACC = 0 skips next instruction execution
Impact Flag None
8. unconditional transfer
1 interconnect (TV-12p)
Instruction Description The contents of the program counter are unconditionally replaced by the specified address, and the program continues to execute at the new address. When
When the new address is loaded, an empty instruction cycle must be inserted, so this instruction is a 2-cycle instruction.
Function Representation Program Counter & larr; k
Impact Flag None
2 GATO k
The instruction description unconditionally calls the subroutine at the specified address, at which point the program counter is first increased by 1 to obtain the next to be executed.
The instruction address is pushed onto the stack, then the specified address is loaded and the program continues from the new address, as this instruction requires an amount
external operation, so it is a 2-cycle instruction.
功能表示Stack ← Program Counter 1
Program Counter ← k
Impact Flag None
3、RET
The instruction description restores the program counter value in the stack register, and the program continues execution from the retrieved address.
功能表示Program Counter ← Stack
Impact Flag None
4、RETL k
The instruction description restores the program counter value in the stack register and the accumulator loads the specified immediate number, which is retrieved by
address to continue execution.
功能表示Program Counter ← Stack
ACC ← k
Impact Flag None
5、RETIN
The instruction shows that the program counter value in the stack register is restored and the interrupt function is re-enabled by setting the GIE bit. GIE
is the main control bit that controls interrupt enable. If there is an interrupt that has not been corresponding before the RETIN instruction is executed, this interrupt
will be corresponding before returning to the main program.
功能表示Program Counter ← Stack
EMI ← 1
Impact Flag None
9. other instructions
1、NOP
The instruction describes a null operation, followed by sequential execution of the next instruction.
Functional Representation PC & larr; PC 1
Impact Flag None
2、CLR A
The instruction description clears the contents of the work register ACC.
Function Representation m & larr; 00H
Impact Flag None
3、CLR m
The instruction description zeroes out the contents of the specified data memory.
Function Representation m & larr; 00H
Impact Flag None
4、SET m
The instruction description sets each bit of the specified data memory to 1.
Function Representation m & larr; FFH
Impact Flag None
5、CLRWDT
Instruction Description The WDT counter, pause flag PDF, and watchdog overflow flag TO are cleared.
Function Representation WDT & larr; 00H
TO & PDF ← 0
Impact flag bit TO, PDF
6、CLRWDT1
Instruction Description Clear WDT Timer, PDF and TO remain unchanged.
Function Representation WDT & larr; 00H
7、SWOP m,0
The instruction description exchanges the lower 4 bits and the upper 4 bits of the designated data memory with each other.
Function representation m.3 ~ m.0 & harr; m.7 ~ m.4
Impact Flag None
8、SWOP m,1
The instruction description exchanges the low 4 bits of the specified data memory with the high 4 bits, and then stores the results in the accumulator and specifies.
The data of the data register remains unchanged.
Function means ACC. 3~ACC. 0 ← m.7~m.4
ACC.7~ACC.4 ← m.3~m.0
Impact Flag None
9、STOP
Instruction Description This instruction terminates program execution and turns off the system clock. The contents of RAM and registers remain in their original state,
The WDT counter and divider are cleared to "0", the pause flag PDF is set to 1, and the WDT overflow flag TO is cleared
0。
Functional representation TO & larr; 0
PDF ← 1
影响标志位 TO、PDF
6. Application Areas
With its low power consumption, high integration and rich peripheral resources, CXMC33129 is suitable for the following fields:
◆ Intelligent sensor nodes (temperature and humidity, pressure, light, etc.)
◆ Portable medical equipment (sphygmomanometer, thermometer)
◆ Industrial control and acquisition system
◆ Control of household appliances
◆ Internet of Things terminal equipment
7. electrical characteristics
7.1. Limit parameters
7.2. Electrical characteristics
8. Summary
CXMC33129 is a full-featured, balanced-performance 8-bit RISC microcontroller, especially for embedded applications that require power and precision. Its dual ADC design, temperature sensor and multi-mode support make it stand out in the competitive MCU market. Both beginners and senior engineers can quickly develop high-performance, low-power embedded systems based on CXMC33129.
If there are any other requirements, please feel free to let me know and we will adjust together.
9. Related Products
| Model | Characteristics | SRAM | OTP space | ADC | IO control port | Timer | Interrupt Source | PWM | Encapsulation form | Remarks |
| CXMC33127 | OTP MCU | 256byte | 8k*16bit | 24bit two channels/8bit * 1 | 8 | 1 | 5 | 2 | SSOP48 | LCD with 18*4 |
| CXMC33128 | OTP MCU | 256byte | 8k*16bit | 24bit two channels/8bit * 1 | 11 | 1 | 5 | 2 | SOP20 | |
| CXMC33129 | OTP MCU | 256byte | 8k*16bit | 24bit two channels/8bit * 1 | 10/13 | 1 | 5 | 2 | SOP16/SOP20 | |
| Model | Characteristics | SRAM | OTP space | ADC | IO control port | Timer | Interrupt Source | PWM | Encapsulation form | |
| CXMC33130 | OTP MCU | 256byte | 8k*16bit | 24bit * 100.00g channel/8bit * 1 | 11 | 2 | 5 | 2 | SOP20 | (Special for Pricing Scale) |
