• [ CXHA31128 ]"

Ordering

CXHA31128 H-bridge DC motor driver chip detailed explanation and application guide

          CXHA31128 is a high-performance, low-power DC brushed motor driver chip that integrates an H-bridge circuit structure and uses N-channel and P-channel power MOSFET designs. It has rich protection functions and a flexible I2C control interface. This chip is suitable for scenarios such as smart locks, toys, and consumer electronics that require high power consumption and space. This article will comprehensively analyze its functional characteristics, electrical parameters, control protocols, and practical application solutions.mxs嘉泰姆

1、 Product Overview and Functional Features

        CXHA31128 supports a wide voltage input of 2.8V~9.5V, with extremely low standby current (<0.1μ A) and static working current. It integrates soft start function, which can effectively suppress current surge during motor startup. Its main features include:mxs嘉泰姆

1.1. Low power designThe standby current is only 14nA, and the static current is as low as 305 A;mxs嘉泰姆

1.2. Integrated H-bridge driverSupports four working modes: forward rotation, reverse rotation, braking, and standby;mxs嘉泰姆

1.3. Multiple protection mechanismsIncluding under voltage lockout (UVLO), over-current protection (OCP), and over temperature protection (OTP);mxs嘉泰姆

1.4. Soft start functionGradual PWM duty cycle from 0% to 100% takes 16ms to smoothly start the motor;mxs嘉泰姆

1.5. Dual packaging optionsSOP8 and SOT23-6, adapted to different layout requirements;mxs嘉泰姆

1.6.I2C Control InterfaceSupports standard I2C protocol, built-in pull-up resistor, simplifies external circuits.mxs嘉泰姆

2、 Pin Function and Packaging Description

2.1.SOP8 Package Pin Definition:

2.2 SOT23-6 Package Pin Definition:

3、 Electrical characteristics and working conditions

3.1. Limit parameters:

3.2. Recommended working conditions:

3.3. Electrical characteristics (T=25 ℃, VDD=6V):

4、 I2C Communication Protocol and Control Register

CXHA31128 is controlled through the I2C interface and supports standard start/stop conditions and ACK response mechanisms. The slave address is 0x6C and supports the following registers:mxs嘉泰姆
      This chip uses the I2C protocol 2-wire serial interface for data transmission, which includes a serial data line SDA and a clock linemxs嘉泰姆
SCL， Two wire built-in pull-up resistor, which is at high level when the bus is idle.mxs嘉泰姆
      Each time data transmission occurs, the controller generates a start signal and uses synchronous serial data transmission. CXHA31128 is connected to each othermxs嘉泰姆
After receiving one byte of data, respond with an ACK response signal. Each byte sent to the SDA line must be 8 bitsmxs嘉泰姆
The number of bytes that can be sent in a second transmission is not limited. Each byte must be followed by an ACK response signal, unless otherwise requiredmxs嘉泰姆
When an ACK signal is received, the SCL signal is used as a reference; 8 signal falling edges to the th; 9 signals need to be input at a low level until the falling edgemxs嘉泰姆
“ L”。 After the data is transmitted from the highest bit, the controller terminates the bus transmission by generating a stop signal, and the datamxs嘉泰姆
If the start signal is resent during the sending process, there is no need to go through the stop signal.mxs嘉泰姆
      When SCL is at a high level, the data on SDA remains stable; When SCL is low, SDA is allowed to change. If SCLmxs嘉泰姆
When at a high level, a falling edge is generated on SDA, which is considered as the starting signal; If SCL is at high level, on SDAmxs嘉泰姆
The rising edge generated is considered as a stop signal. As shown in the above figure.mxs嘉泰姆

4.1. Control register (address 0x95):

4.2. Functional Truth Table:mxs嘉泰姆

4.3. PCT_CTL register (address 0x96):

Used to enable or disable overcurrent protection function (D0 bit: 1=on, 0=off).mxs嘉泰姆
mxs嘉泰姆
4.4. Data Registermxs嘉泰姆
mxs嘉泰姆
4.5. Data Structuremxs嘉泰姆

(1) Formation of starting conditionsmxs嘉泰姆
(2) Send Slave Address;mxs嘉泰姆
(3) Register address, display data transfermxs嘉泰姆
(4) Establish stop conditionsmxs嘉泰姆
mxs嘉泰姆

4.6. Temporal Characteristicsmxs嘉泰姆
mxs嘉泰姆

5、 Typical Application Circuit

The following figure shows a typical application circuit of CXHA31128, packaged in SOP8 and controlled through the I2C interface of the MCU:mxs嘉泰姆
mxs嘉泰姆

[Illustration: VDD connected to 4.7K pull-up resistor to MCU_VCC, SDA and SCL connected to 4.7K pull-up resistor respectively and then connected to MCU, OUTP and OUTN connected to DC motor]

6、 Package size description

6.1.SOP8Size 5.0× 4.0mm， Pin spacing of 1.27mm, suitable for designs with ample space;mxs嘉泰姆
mxs嘉泰姆

6.2.SOT23-6The size is 3.0× 1.6mm， Pin spacing of 0.95mm, suitable for high-density PCB layout.mxs嘉泰姆
mxs嘉泰姆

7、 Precautions for use

7.1. Power filteringSuggest parallel connection of 100nF and 10μ F capacitors between VDD and GND to suppress noise;mxs嘉泰姆

7.2. Heat dissipation designWhen the continuous output current exceeds 300mA, heat dissipation measures should be considered;mxs嘉泰姆

7.3.I2C WiringSDA and SCL lines should be kept as short as possible to avoid parallel high-speed signal lines;mxs嘉泰姆

7.4. Ground wire separationSuggest single point grounding of power ground (GNDB) and logic ground (GNDA) near the chip.mxs嘉泰姆

8、 Conclusion

      CXHA31128 is an ideal choice for driving DC brushed motors in applications such as smart locks, toys, and portable devices due to its low power consumption, high integration, flexible I2C control, and comprehensive protection functions. Developers can use the technical information provided in this article to quickly complete system design, enhance product reliability and market competitiveness.mxs嘉泰姆

◀ Previous:CXHA31127 Dual Channel Inverted Output Motor Driver Chip - High Frequency Vibration Motor Driver Solution

Back to top

Next▶:CXHA31129 haptic feedback driver: Efficient ERM motor driver chip | Low latency, wide voltage, portable device preferred