• [ CXLE87141A ]"

Ordering

In today's increasingly widespread application of LED lighting and decoration, efficient, stable and easy-to-control driver chips have become the core of product design. As a high-performance single-line three-channel LED constant current driver chip, with its excellent integration and flexible communication mode, CXLE87141A is gradually becoming the preferred driving scheme for LED decoration products such as guardrail tube, point light source, RGB light bar and so on. This article will provide an in-depth analysis of the CXLE87141A's technical features, application scenarios, and optimization recommendations to help engineers and purchasers better understand and select the chip.KPW嘉泰姆

1. Product Overview and Technical Highlights

CXLE87141A is a single-wire three-channel LED constant current driver chip manufactured by power CMOS process. Its biggest feature is that it supports dual-channel digital interfaces (DIN and FDIN) to switch inputs to each other, and realizes data cascade transmission through the DO port, so that the external controller can realize precise control of multiple chips with only a single line. The chip integrates MCU single-wire dual-channel digital interface, data latch, LED constant current drive, PWM brightness control and other modules, and the VDD pin has a built-in 5V regulator, which greatly simplifies the design of peripheral circuits.KPW嘉泰姆

Its key technical highlights include:KPW嘉泰姆

•   High withstand voltage output: OUT port withstand voltage up to 24V, suitable for a variety of voltage environment;KPW嘉泰姆

•   Accurate constant current output: Fixed output 18mA, inter-channel error ≤ ± 3%, inter-chip error ≤ ± 5%;KPW嘉泰姆

•   256-level brightness adjustmentSupport PWM dimming, to achieve delicate light effect control;KPW嘉泰姆

•   automatic signal shaping and forwarding: The data is not distorted or attenuated during the cascade process;KPW嘉泰姆

•   Wide voltage power supplyVDD support 6~24V input, adapt to a variety of power supply scheme.KPW嘉泰姆

2. Package and Pin Function

The CXLE87141A is packaged in SOP8, which is small in size and easy to integrate. The functions of each pin are as follows:KPW嘉泰姆

•   DIN (pin 5): Master data input;KPW嘉泰姆

•   FDIN (Pin 7): Standby data entry;KPW嘉泰姆

•   DO (Pin 4): Data output for cascading the next chip;KPW嘉泰姆

•   OUTR/OUTG/OUTB（引脚1-3）: Three-way N-tube open-leakage constant current output;KPW嘉泰姆

•   VDD (pin 8): Positive pole of power supply;KPW嘉泰姆

•   GND (pin 6): Power supply ground.KPW嘉泰姆

3. working mode and data protocol

The chip supports three modes of operation, which are configured by the 48-bit mode setting command:KPW嘉泰姆

3.1. Normal working mode(Command: 0xFFFFFF_000000):DIN and FDIN automatically switch input to improve system fault tolerance;KPW嘉泰姆

3.2. DIN working mode(Command: 0xFFFFFA_000005): Accept DIN input only;KPW嘉泰姆

3.3. FDIN Operating Mode(Command: 0xFFFFF5_000004): Accept FDIN input only.KPW嘉泰姆

Each chip receives 24 bits of display data (R, G, B each 8 bits) and forwards subsequent data through the DO port. The Reset signal (high level ≥ 200 μs) is used to trigger the output update to complete the refresh of one frame of data.KPW嘉泰姆

4. Typical Application Circuits and Design Recommendations

KPW嘉泰姆
Note: If the controller has only one signal port, the FDIN of the first point is suspended, DIN is connected to the controller, and the other points are connected as shown above.KPW嘉泰姆
In order to prevent the signal input and output pins of the chip from being damaged due to the instantaneous high voltage generated by the live plug and pull of the product during the test, the signal input andKPW嘉泰姆
The output pin is connected in series with a 100Ω protection resistor. In addition, the 104 decoupling capacitors of each chip in the figure are indispensable, and the VDD and GND traces to the chip areKPW嘉泰姆
The feet should be as short as possible to achieve the best decoupling effect and stabilize the chip work.

4.1. Power Configuration

The CXLE87141A can be configured as DC6 ~ 24V voltage power supply, but according to the input voltage, different power supply resistance and resistance meter should be configuredKPW嘉泰姆
Calculation method: VDD port current is calculated by 10mA, VDD series connection resistor R =(DC-5.5V)÷ 10mA(DC is power supply voltage).KPW嘉泰姆
Typical values of the configured resistors are listed below:KPW嘉泰姆

According to the power supply voltage (DC 6~24V), the current limiting resistor should be connected in series before VDD, and the calculation formula is as follows:KPW嘉泰姆

Typical resistance values are as follows:KPW嘉泰姆

•   6V & rarr; 50ΩKPW嘉泰姆

•   9V & rarr; 350ΩKPW嘉泰姆

•   12V & rarr; 650ΩKPW嘉泰姆

•   24V & rarr; 1.8kΩKPW嘉泰姆

4.2. Constant current optimization design.

In order to ensure that the chip works in the best constant current state, the OUT port voltage is recommended to be controlled between 1.2~3V. If the voltage is too high, it can be reduced by series resistance:KPW嘉泰姆

For example, if a 24V system drives 6 LEDs (each with a voltage drop of 2V), then:KPW嘉泰姆

4.3. Expanding flow applications.

If a larger drive current is required, the three ports of OUTR, OUTG and OUTB can be short-circuited, and the maximum output current can reach 54mA. The software needs to configure three sets of PWM registers synchronously to achieve precise control.KPW嘉泰姆
CXLE87141A each OUT port constant output 18mA current, if the user needs to expand the drive current, the RGB three OUT ports can be shortedKPW嘉泰姆
After use, the maximum constant current value will increase by 18mA for each OUT port shorted, and the maximum constant current value can reach 54mA after all three OUT ports are shorted.KPW嘉泰姆
This method requires software to cooperate with control at the same time and write three sets of register values respectively, which can realize accurate current control and large driving current.KPW嘉泰姆
KPW嘉泰姆

4.4. Role of different working modesKPW嘉泰姆
During the normal use of the product, the chip should be set to the normal working mode, and the number of data input and DO channels should be switched through DIN and FDIN.KPW嘉泰姆
According to the output, it can effectively prevent the data from being unable to be transmitted normally due to the damage of the data port of a certain chip or even the whole chip.KPW嘉泰姆
During the production aging and installation process, the chip can be set to DIN mode and FDIN mode respectively.KPW嘉泰姆
Chip and line connectivity testing, timely detection of chip damage or poor line connection and other hidden dangers.KPW嘉泰姆
4.5. Constant current curveKPW嘉泰姆
When the CXLE87141A is applied to the design of LED products, the current difference between channels and even between chips is very small, and when the load terminal voltage changesKPW嘉泰姆
The stability of its output current is not affected, and the constant current curve is shown in the following figure:KPW嘉泰姆

KPW嘉泰姆

4.6. Input and output equivalent circuitKPW嘉泰姆

KPW嘉泰姆

5. data refresh rate calculation

The system refresh rate is directly related to the number of pixel dots. Take the 800kHz data rate as an example:KPW嘉泰姆

•   24bit per pixel, transmission time: 1.25μs × 24 = 30μs;KPW嘉泰姆

•   Refresh time of 1000 pixel system: 30μs × 1000=30ms;KPW嘉泰姆

•   Refresh rate: 1 ÷ 30ms & asynmp; 33Hz.KPW嘉泰姆

The following table is a reference for the refresh rate corresponding to common points:KPW嘉泰姆

6. anti-static and welding precautions

CXLE87141A are electrostatic sensitive devices, it is recommended to take anti-static measures in a dry environment. Welding should avoid high temperature contact for a long time, to prevent ESD damage or performance degradation.KPW嘉泰姆

7. electrical characteristics

7.1. Limit parameters

KPW嘉泰姆
(1) These levels in the above table, the chip may cause permanent damage to the device and reduce the reliability of the device under long-term use conditions. We do not recommend in itsKPW嘉泰姆
It works under any condition that the chip exceeds these limit parameters;KPW嘉泰姆
(2) All voltage values are tested relative to the system ground.KPW嘉泰姆
7.2. Recommended working conditionsKPW嘉泰姆
KPW嘉泰姆
7.3. Electrical characteristicsKPW嘉泰姆
KPW嘉泰姆
7.4. Switching characteristicsKPW嘉泰姆
KPW嘉泰姆
7.5. Timing characteristicsKPW嘉泰姆
KPW嘉泰姆
(1)0 code or 1 code cycle in the 1.25 μs (frequency 800KHz) to 2.5 μs (frequency 400KHz) range, the chip can work normally, but 0 code and 1KPW嘉泰姆
The code low level time must conform to the corresponding numerical range in the above table;KPW嘉泰姆
(2) When there is no need to reset, the high-level time between bytes should not exceed 50μs, otherwise the chip may reset and receive data again after reset, which cannot realize dataKPW嘉泰姆
Transmit correctly.KPW嘉泰姆

8. Function Description

8.1. Mode setting

The chip is a single-line dual-channel communication, using a normalized code to send signals. The chip needs to be configured to work correctly before receiving the display dataKPW嘉泰姆
Mode to select how to receive display data. The mode setting command is 48bit in total, of which the first 24bit is the command code and the last 24bit is the check inverse code,KPW嘉泰姆
The chip reset starts to receive data, and there are three mode setting commands as follows:KPW嘉泰姆
(1)0xFFFFFF_000000 command:KPW嘉泰姆
The chip is configured for normal operation mode. In this mode, the default DIN receives display data for the first time, and the chip detects that the port has a signal input.KPW嘉泰姆
If no data is received for more than 300ms, switch to FDIN to receive display data, and the chip detectsKPW嘉泰姆
If the port has a signal input, it will keep receiving the port all the time. If no data is received for more than 300ms, it will switch to DIN to receive the display data again.KPW嘉泰姆
DIN and FDIN are cyclically switched to receive display data.KPW嘉泰姆
(2)0xFFFFFA_000005 command:KPW嘉泰姆
The chip is configured for DIN operation mode. In this mode, the chip only receives the display data input from the DIN terminal, and the FDIN terminal data is invalid.KPW嘉泰姆
(3)0xFFFFF5_00000A command:KPW嘉泰姆
The chip is configured for FDIN mode of operation. In this mode, the chip only receives the display data input from the FDIN terminal, and the DIN terminal data is invalid.KPW嘉泰姆
8.2 display dataKPW嘉泰姆
After the chip is powered on and reset and receives the mode setting command, it starts to receive display data. After receiving 24bit, the DO port starts to forward DINKPW嘉泰姆
Or the FDIN terminal continues to send data to provide display data for the next cascade chip. The DO port is high until the data is forwarded. SuchKPW嘉泰姆
If the Reset reset signal is input to the DIN or FDIN terminal, the chip OUT port will output the PWM of the corresponding duty cycle according to the received 24-bit display data.KPW嘉泰姆
Waveform, and the chip waits to receive new data again. After receiving the starting 24bit data, the chip forwards the data through the DO port.KPW嘉泰姆
The original OUTR, OUTG, and OUTB outputs remain unchanged until the Reset signal is received.KPW嘉泰姆
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted and attenuated. For all chips cascaded together, the period of data transmission isKPW嘉泰姆
Consistent.KPW嘉泰姆
8.3. A frame of complete data structure.KPW嘉泰姆

KPW嘉泰姆
     C1 and C2 are mode setting commands, each containing 24bit data bits. Each chip will receive and forward C1 and C2, of which 0xFFFFFF_000000KPW嘉泰姆
is the normal operating mode command, 0xFFFFFA_000005 is the DIN operating mode command, and 0xFFFFF5_00000A is the FDIN operating mode command.KPW嘉泰姆
D1, D2, D3, D4,..., Dn have the same data format, D1 represents the display data packet of the first chip in cascade, Dn represents the n-th chip in cascadeKPW嘉泰姆
Chip display data packets, each display data packet contains 24-bit data bits. Reset represents a reset signal, and the high level is active.KPW嘉泰姆

8.4. The data format of Dn.KPW嘉泰姆

KPW嘉泰姆
Each display packet contains 8 × 3 bits of data, with the upper bits first.KPW嘉泰姆
R[7:0]: Used to set the PWM duty cycle of the OUTR output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.KPW嘉泰姆
G[7:0]: Used to set the PWM duty cycle of the OUTG output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.KPW嘉泰姆
B[7:0]: Used to set the PWM duty cycle of the OUTB output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.KPW嘉泰姆

8.5. Data receiving and forwardingKPW嘉泰姆

KPW嘉泰姆

S1 is data sent by the Di port of the controller, and S2, S3, and S4 are data forwarded by the cascade CXLE87141A.KPW嘉泰姆
Controller Di and Fi2 port data structures: C1C2D1D2D3D4... Dn;KPW嘉泰姆
Controller Fi port data structure: C1C2DxD1D2D3... Dn;KPW嘉泰姆
Wherein, Dx is any 24bit data bit.KPW嘉泰姆

KPW嘉泰姆
Chip cascade and data transmission and forwarding process is as follows: the controller sends data S1, chip 1 receives C1 and C2 for verification, if the commandKPW嘉泰姆
Correct, forward C1 and C2, while absorbing D1. If there is no Reset reset signal at this time, chip 1 will always forward the controller to continue to sendKPW嘉泰姆
Data; Chip 2 also receives C1 and C2 for verification. If the command is correct, it forwards C1 and C2 and absorbs D2 at the same time. If there is no Reset at this timeKPW嘉泰姆
Reset signal, chip 2 will always forward the data that chip 1 continues to send. And so on, until the controller sends a Reset reset signal, allKPW嘉泰姆
The chip will reset and control the OUT port output after decoding the 24bit display data received respectively, completing a data refresh cycle.KPW嘉泰姆
Return to receive ready. The Reset high level is valid, the holding high level time is greater than 200 μs, and the chip is reset.KPW嘉泰姆

9. epilogue

With its high integration, high precision constant current output, flexible communication mode and powerful cascade capability, CXLE87141A has become an ideal driver chip in the field of LED decorative lighting. Whether it is urban lighting, architectural contour lighting, or interior decoration lighting, the chip can provide stable, reliable and efficient solutions.KPW嘉泰姆

For more information on the technical details of the CXLE87141A, sample application or procurement information, welcome to visitJTM-IC official websiteOr contact our technical support team. JTM-IC are committed to providing customers with high-quality integrated circuit products and professional technical services to help your project success.KPW嘉泰姆

◀ Previous:CXLE87203 single-wire three-channel LED driver chip | ultra-low power consumption | 4096 level dimming | JTM-IC professional supply

Back to top

Next▶:CXLE86135E single-segment high-voltage linear constant-current LED driver chip-JTM-IC thyristor dimming scheme without electrolytic capacitor