CXLE87203 is a single-wire three-channel LED constant current driver chip based on power CMOS process. Its biggest feature is to support DIN and FDIN dual-channel digital input interface, and can realize data cascade transmission through DO port. Even if a chip is damaged in the cascade link, it does not affect the normal operation of subsequent chips, which greatly improves the stability and fault tolerance of the system.
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[ CXLE87203 ]"
Today, with the continuous upgrading of intelligent lighting and LED decoration applications, higher requirements are put forward for the performance, power consumption and system reliability of the driver chip. As a high-performance, low-power single-line three-channel LED constant current driver chip, CXLE87203 has become an ideal choice for point light source, guardrail tube, RGB light strip and other scenes with its excellent integrated design, flexible communication mechanism and ultra-low standby power consumption. This paper will comprehensively analyze the core advantages of the CXLE87203 from technical characteristics, application design to system optimization, and provide professional reference for engineers and procurement personnel.
1. product overview and technical advantages
CXLE87203 is a single-wire three-channel LED constant current driver chip based on power CMOS process. Its biggest feature is to support DIN and FDIN dual-channel digital input interface, and can realize data cascade transmission through DO port. Even if a chip is damaged in the cascade link, it does not affect the normal operation of subsequent chips, which greatly improves the stability and fault tolerance of the system.
The chip integrates MCU single-wire dual-channel digital interface, data latch, LED constant current drive, PWM brightness control and other core circuits, VDD pin built-in 5.5V voltage regulator circuit, supports 9~12V wide voltage input, peripheral circuit is simple, suitable for a variety of LED decoration products.
Key technical advantages include：
• Fixed 12mA constant current output, High output accuracy and excellent consistency;
• PWM luminance control supports 4096 gray levels, the light effect transition is more delicate;
• Ultra-Low Power Standby Mode, Automatically enter the power saving state when there is no signal;
• OUT port withstand voltage 12VAdapt to a variety of load environments;
• Support 800KHz high-speed data transmission, automatic signal shaping, cascade without attenuation;
• Provide SOP8, flip chip and wick integration and other packaging, adapt to different integration needs.
2. Package and Pin Definition
The CXLE87203 is packaged in SOP8 with compact pin arrangement, which is convenient for PCB layout and welding. The functions of each pin are as follows:
| Pin Name | Pin serial number | Function Description |
|---|---|---|
| VDD | 1 | Power supply positive |
| OUTR | 2 | Red channel constant current output |
| OUTG | 3 | Green channel constant current output |
| OUTB | 4 | Blue channel constant current output |
| DO | 5 | data output for cascading |
| GND | 6 | Power Ground |
| DIN | 7 | Master Data Input |
| FDIN | 8 | Standby data entry |
3. core functions and communication protocols
3.1. Data receiving and forwarding mechanism.
The chip starts to receive display data after power-on reset, and after each 24-bit data is received, the DO port starts to forward subsequent data to ensure that each chip in the cascade system can correctly obtain corresponding data. The Reset signal (low level ≥ 200 μs) is used to trigger the output update to complete the refresh of one frame of data.
3.2. Low power standby mode
CXLE87203 features intelligent power management:
• If the received 24bit display data is all 0, the chip automatically enters the low-power standby mode;
• If the DIN/FDIN signal is not received for more than 1 second, the chip will automatically enter the low-power mode;
• In the standby mode, the chip power consumption is very low, which effectively reduces the overall energy consumption of the system.
3.3. Data format and dimming control
The 24bit display data format received by each chip is as follows:
R7 R6 R5 R4 R3 R2 R1 R0 | G7 G6 G5 G4 G3 G2 G1 G0 | B7 B6 B5 B4 B3 B2 B1 B0
• R7:07:0, G7:07:0, B7:07:0 respectively control the PWM duty cycle of OUTR, OUTG, OUTB;
• Support 256 level dimming, all 0 is off, all 1 is the maximum brightness;
• Precise color and brightness control is achieved through a high-order-first serial protocol.
4. Typical Application Circuits and Design Recommendations
4.1. Power Configuration
The CXLE87203 supports DC 9~12V power supply, and the VDD port needs to be connected in series with a current limiting resistor. The calculation formula is as follows:
A typical configuration is as follows:
| Power supply voltage | Series resistance value |
|---|---|
| 5V | No resistance required |
| 9V | 350Ω |
| 12V | 680Ω |
4.2. Signal protection and decoupling design
In order to prevent chip damage caused by live plugging, it is recommended to connect 100Ω protection resistors in series with DIN, FDIN, DO and other signal ports. At the same time, 104(0.1 μF) decoupling capacitors should be connected between VDD and GND of each chip, and the traces should be as short as possible to improve system stability.
4.3. Constant current optimization and resistance selection
In order to ensure that the chip works in the best constant current state, the OUT port voltage is recommended to be controlled between 1.2~3V. If the voltage is too high, it can be reduced by series resistance:
For example, if a 12V system drives 3 LEDs (each with a voltage drop of 2V), then:
If the lamp bar is longer and the voltage drop is larger, the constant current voltage can be appropriately increased to 3V and the resistance value can be recalculated.
The CXLE87203B is driven by constant current. According to the constant current curve, when the OUT port voltage reaches 0.8V, it will enter the constant current state. But not electricity.
The higher the voltage, the higher the voltage, the greater the power consumption of the chip, the more serious the heat, reducing the reliability of the entire system. Recommended OUT port open
The on-time voltage is more appropriate between 1.2~3V, and the excessive voltage of the OUT port can be reduced by connecting resistors in series. The following are selected
calculation of resistance:
System drive voltage: DC
Single LED conduction voltage drop: Vled
Number of series LEDs: n
Constant current value: Iout
Constant current voltage: 1.5V
Resistance: R
R =(DC-1.5V -Vled× n) id=Iout
Example: system power supply: DC12V, single LED conduction voltage drop: 2V, number of series LEDs: 3, constant current value: 12mA, according to the above formula
The calculation can be obtained as follows: R =(12V-1.5V-2V × 3)÷ 12 mA & asymp;375 Ω, only need to connect a resistor of about 375Ω in series at OUT port. Actual
In application, when the light bar is long, VCC will drop at a position far away from the power access point. If the voltage of R/G/B port does not reach the constant current turning point
Voltage, the output will not reach the rated constant current value, at this time can be increased by increasing the constant current voltage value, such as to 3V, can reduce the above
The impact of the lamp, or the project to increase the power access point, to ensure that the supply voltage drop is small.
4.4. Expanding flow applications.
If a larger driving current is required, the three ports of OUTR, OUTG and OUTB can be short-circuited. For each port short-circuited, the maximum output current increases by 12mA, and the maximum output can reach 36mA after the three ports are fully short-circuited. The software needs to configure three sets of PWM registers synchronously to achieve precise control.
4.5. Constant current curve
4.6. Internal structure block diagram
5. data refresh rate calculation
The system refresh rate is closely related to the number of pixel points. Take the 800kHz data rate as an example:
• 24bit per pixel, transmission time: 1.25μs × 24 = 30μs;
• Refresh time of 1000 pixel system: 30μs × 1000=30ms;
• Refresh rate: 1 ÷ 30ms & asynmp; 33Hz.
The corresponding refresh rate of common points is as follows:
| Pixel Points | Refresh Time (ms) | Refresh Rate (Hz) |
|---|---|---|
| 1~400 | 12 | 83 |
| 1~800 | 24 | 41 |
| 1~1000 | 30 | 33 |
The data refresh time is calculated based on how many pixels are cascaded in a system, and a set of RGB is usually one pixel (or one
segment), a CXLE87203B chip can control a set of RGB.
Calculated according to normal mode:
1bit data cycle is 1.25 μs (frequency 800KHz), a pixel data including R(8bit), G(8bit), B(8bit)
A total of 24bit, the transmission time is 1.25μs × 24 = 30μs. If there are 1000 pixels in a system, refresh all the display at once
The time of is 30μs × 1000=30ms (ignoring Reset signal time), I .e. the refresh rate of one second is: 1 ÷ 30ms & asymp;33Hz.
The following is a table of the maximum data refresh rate for the number of cascade points:
6. anti-static and welding precautions
CXLE87203 for electrostatic sensitive devices, in a dry environment to take anti-static measures. Temperature and time should be controlled during welding to avoid ESD damage or performance degradation.
7. operating parameters Electrical characteristics
7.1. Limit parameters
(1) These levels in the above table, the chip may cause permanent damage to the device and reduce the reliability of the device under long-term use conditions.
We do not recommend that the chip work beyond these limit parameters under any other conditions;
(2) All voltage values are tested relative to the system ground.
7.2. Recommended working conditions
7.3. Electrical characteristics
7.4. Switching characteristics
7.5 timing characteristics
7.6 Function Description
After the chip is powered on and reset, it starts to receive display data. After receiving 24bit, DO port starts to forward the continuous transmission from DIN or FDIN terminal.
Data to provide display data for the next cascade chip. The DO port is low until the data is forwarded. If DIN or FDIN input
Reset reset signal, the chip OUT port will output the PWM waveform of the corresponding duty cycle according to the received 24-bit display data, and the chip will re-
Waiting to receive new data, after receiving the starting 24bit data, the chip forwards the data through the DO port, and the chip does not receive the Reset message
The original output of OUTR, OUTG and OUTB remains unchanged. The chip has a low-power standby mode, if the received 24bit display data full
0, the chip enters a low-power standby mode; if the received 24-bit display data is not all 0, the chip enters a normal mode. When the core
If the chip does not receive DIN/FDIN display data for more than 1s, the chip will automatically enter low power consumption mode. In low-power mode, the chip is connected.
Received normal non-all 0 data frames will enter the normal mode for display output.
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted and attenuated. For all chips cascaded together, the period of data transmission
is consistent.
D1, D2, D3, D4,..., Dn have the same data format, D1 represents the display data packet of the first chip in cascade, Dn represents the first chip in cascade
N chip display data packet, each display data packet contains 24bit data bits. Reset represents a reset signal, and the low level is active.
7.6.2 Data format of Dn
Each display packet contains 8 × 3 bits of data, with the upper bits first.
R[7:0]: Used to set the PWM duty cycle of the OUTR output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.
G[7:0]: Used to set the PWM duty cycle of the OUTG output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.
B[7:0]: Used to set the PWM duty cycle of the OUTB output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.
7.6.3 Data Receiving and Forwarding
S1 is data sent by the Di port of the controller, and S2, S3, and S4 are data forwarded by the cascade CXLE87203B.
Controller Di and Fi2 port data structures: D1D2D3D4... Dn;
Controller Fi port data structure: DxD1D2D3D4... Dn; where Dx is any 24-bit data bit.
The data receiving and forwarding process during chip cascade is as follows: the controller sends data packet D1, chip 1 receives the first set of 24bit, at this time the core
Chip 1 has no forwarding; Then the controller sends the data packet D2, and chip 1 receives the second set of 24bits, because chip 1 already has the first set.
24bit, therefore, chip 1 forwards the second set of 24bit to chip 2 through DO, and chip 2 receives the data packet D2 forwarded by chip 1. This
When chip 2 does not forward; Then the controller sends the data packet D3, and chip 1 forwards the received third group of 24bits to chip 2, because the core
Chip 2 already stores the second group of 24bits, so chip 2 forwards the third group of 24bits to chip 3, and chip 3 receives the third group
24bit; and so on, all chips in the cascade will get their own display data. At this time, if the controller sends a Reset signal,
Some chips will reset and control the output of OUT port after decoding the 24bit data received respectively, completing a data refresh cycle.
Return to receive ready. Reset is active at low level, the holding time at low level is greater than 200 μs, and the chip is reset.
EightConclusion
With its low power consumption, high gray scale, strong fault tolerance and other characteristics, CXLE87203 has become the preferred driver chip in the field of LED decorative lighting. Whether it is urban lighting, architectural outline lighting, or interior decoration lighting, the chip can provide stable, efficient and energy-saving drive solutions.
For CXLE87203 samples, technical information or procurement support, welcome to visitJTM-IC official websiteOr contact our technical support team. JTM-IC are committed to providing high-quality integrated circuit products and professional services to customers around the world to help your project succeed.
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| Single line series | |||||||
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| CXLE87140H | 24V | 3 | Return to 0 | 14mA | 256 | SOP8 | LED decorative driver chip, single line series |
| CXLE87132B | 32V | 4 | Return to 1 | 6.5-38mA | 256 | SOP8 | LED decorative driver chip, single line series |
| CXLE87143D | 24V | 6 or 9 | Return to 0 | 17mA | 256 | SOP14/DIP14 | LED decorative driver chip, single line series |
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| CXLE87143 | 30V | 9 | Return to 1 | 20mA | 256 | SOP14/DIP14 | LED decorative driver chip, colorful internal control, single line series |
| CXLE87140 | 24V | 3 | Return to 1 | 18mA | 256 | SOP8/MSOP8 | LED decorative driver chip, colorful internal control, single line series |
| CXLE87132 | 32V | 4 | Return to 1 | 6.5-38mA | 256 | SOP8 | LED decorative driver chip, colorful internal control, single line series |
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| CXLE87145 | 24V | 9 | Return to 0 | <45mA | 256 | SOP14/DIP14 | LED decorative driver chip, constant voltage, single line series |
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| constant current diode | |||||||
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| Meteor lights Christmas lights | |||||||
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| CXLE87137 | 24V | 12 | Internal/external control | 32mA | - | SOP16/DIP16 | LED decoration driver chip, meteor lights Christmas lights |
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| CXLE87150 | 24V | 12 | internal control | 45, maximum 90mA | Level 16 | SOP16/DIP16 | LED decoration driver chip, meteor lights Christmas lights |
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