• [ CX74HC164 ]"

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1.产品概述       2.产品特点     95Z嘉泰姆

3.应用范围       4.技术规格书下载（PDF文档）95Z嘉泰姆

5.产品封装       6.电路原理图  95Z嘉泰姆

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  These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. 

       The CX54HC164 is characterized for operation over the full military temperature range of –55℃ to 125℃. The  CX74HC164 is characterized for operation from -40℃ to 85℃.95Z嘉泰姆

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AND-Gated (Enable/Disable) Serial Inputs95Z嘉泰姆

Fully Buffered Clock and Serial Inputs  95Z嘉泰姆

Direct Clear95Z嘉泰姆

Package Options Include Plastic95Z嘉泰姆

     Small-Outline (D) and Ceramic Flat (W)95Z嘉泰姆

     Packages, Ceramic Chip Carriers (FK), and95Z嘉泰姆

     Standard Plastic (N) and Ceramic (J) 300-mil DIPS95Z嘉泰姆

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   技术规格书（产品PDF) 返回TOP 95Z嘉泰姆

     需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！95Z嘉泰姆

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Next▶:CX74HC245 These octal bus transceivers are designed for asynchronous two-way communication between data buses The control-function implementation minimizes external timing requirements