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CXLE87201: high-performance single-line three-channel LED constant current driver chip

In the field of LED decorative lighting, such as guardrail tube, point light source, curtain wall lighting and other applications, the stability, flexibility and control accuracy of the driver chip are put forward higher requirements. As a single-line three-channel constant current driver chip designed for LED decorative products, CXLE87201 has become the first choice for many lighting solutions due to its excellent performance and reliable cascade control capability. This article will analyze the functional characteristics, electrical parameters, application scenarios and design suggestions of the CXLE87201 in depth to help engineers better understand and apply the chip.9LB嘉泰姆

1. Product Overview

CXLE87201 is a single-wire three-channel LED constant current driver chip manufactured by power CMOS process. Its biggest feature is to support dual-channel digital interface (DIN and FDIN) to switch the input, and through the DO port to achieve signal cascade transmission. Even if a chip is damaged in the cascade link, it will not affect the normal operation of subsequent chips, which greatly improves the reliability and maintainability of the system.9LB嘉泰姆

The chip integrates MCU single-wire dual-channel digital interface, data latch, LED constant current drive, PWM brightness control and other circuits, which is suitable for 5V power supply scheme. The output current is fixed at 5mA, and the OUT port withstand voltage is as high as 12V. It can be widely used in various RGB LED decorative lighting systems.9LB嘉泰姆

2. core features

•   Single-wire dual-channel serial cascade interface: Support DIN and FDIN dual input switching, DO port forwarding data, signal transmission stability without attenuation;9LB嘉泰姆

•   PWM luminance controlSupport 4096 gray level adjustment, realize smooth color transition and brightness change;9LB嘉泰姆

•   Ultra-Low Power Standby Mode: Automatically enter low power consumption mode when there is no signal or all 0 data state, and the standby current is as low as 150 μA;9LB嘉泰姆

•   High precision constant current output: The output current has high accuracy, good consistency between channels, and is not affected by load voltage fluctuations;9LB嘉泰姆

•   Built-in power-on reset circuit: Ensure that all registers are initialized to zero when the chip starts, and the system works stably;9LB嘉泰姆

•   automatic shaping forwarding technology: The signal is not distorted or attenuated during the cascade process, suitable for long-distance and multi-node applications;9LB嘉泰姆

•   Wide operating temperature range:-40 ℃ to 85 ℃, adapt to harsh environment.9LB嘉泰姆

3. electrical characteristics and operating conditions

The CXLE87201 is stable in the recommended operating voltage range of 4.5V to 6.5V, and the typical application is 5V system. Its DIN/FDIN input high level threshold is 3.5V, low level threshold is 1.0V, with good noise tolerance. The output constant current of OUT port is 5mA, and the leakage current is less than 0.5 μA, which ensures that there is no low light in the off state of LED.9LB嘉泰姆

The chip supports 800KHz data transmission rate, the PWM output frequency is 3.6KHz, and the transmission delay time is only 170ns. It responds quickly and is suitable for dynamic display and high-speed refresh scenarios.9LB嘉泰姆

3.1. Limit parameters9LB嘉泰姆
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(1) These levels in the above table, the chip may cause permanent damage to the device and reduce the reliability of the device under long-term use conditions.9LB嘉泰姆
We do not recommend that the chip work beyond these limit parameters under any other conditions;9LB嘉泰姆
(2) All voltage values are tested relative to the system ground.9LB嘉泰姆
3.2. Recommended working conditions9LB嘉泰姆
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3.3. Electrical characteristics9LB嘉泰姆
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3.4. Switching characteristics9LB嘉泰姆
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4. Time Series and Data Format

The chip uses a single-wire serial communication protocol, each data cycle is 1.25 μs(800KHz), each chip needs to receive 24-bit RGB data (8 bits each), and supports 256-level PWM dimming. The reset signal (Reset) is active low, and the duration needs to be greater than 200 μs to lock the data and update the output.9LB嘉泰姆

The data frame structure is to continuously send 24-bit data packets of each chip, followed by a reset signal. The chip automatically forwards subsequent data after receiving its own data to achieve cascade control. If no valid data is received for more than 1 second, the chip automatically enters a low-power standby mode, which has a significant energy saving effect.9LB嘉泰姆

4.1. Timing characteristics9LB嘉泰姆
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(1)0 code or 1 code cycle in 1.25 μs (frequency 800KHz) to 2.5 μs (frequency 400KHz) range, the chip can work normally9LB嘉泰姆
However, the high level time of 0 code and 1 code must conform to the corresponding numerical range in the above table;9LB嘉泰姆
(2) When reset is not required, the low level time between bytes should not exceed 50μs, otherwise the chip may reset and receive the number again after reset.9LB嘉泰姆
data cannot be transmitted correctly.9LB嘉泰姆
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4.2. Function Description9LB嘉泰姆
After the chip is powered on and reset, it starts to receive display data. After receiving 24bit, DO port starts to forward the continuous transmission from DIN or FDIN terminal.9LB嘉泰姆
Data to provide display data for the next cascade chip. The DO port is low until the data is forwarded. If DIN or FDIN input9LB嘉泰姆
Reset reset signal, the chip OUT port will output the PWM waveform of the corresponding duty cycle according to the received 24-bit display data, and the chip will re-9LB嘉泰姆
Waiting to receive new data, after receiving the starting 24bit data, the chip forwards the data through the DO port, and the chip does not receive the Reset message9LB嘉泰姆
The original output of OUTR, OUTG and OUTB remains unchanged. The chip has a low-power standby mode, if the received 24bit display data full9LB嘉泰姆
0, the chip enters a low-power standby mode; if the received 24-bit display data is not all 0, the chip enters a normal mode. When the core9LB嘉泰姆
If the chip does not receive DIN/FDIN display data for more than 1s, the chip will automatically enter low power consumption mode. In low-power mode, the chip is connected.9LB嘉泰姆
Received normal non-all 0 data frames will enter the normal mode for display output.9LB嘉泰姆
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted and attenuated. For all chips cascaded together, the period of data transmission9LB嘉泰姆
is consistent.9LB嘉泰姆

4.2.1 One frame complete data structure9LB嘉泰姆
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D1, D2, D3, D4,..., Dn have the same data format, D1 represents the display data packet of the first chip in cascade, Dn represents the first chip in cascade9LB嘉泰姆
N chip display data packet, each display data packet contains 24bit data bits. Reset represents a reset signal, and the low level is active.9LB嘉泰姆
4.2.2 Data format of Dn9LB嘉泰姆
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Each display packet contains 8 × 3 bits of data, with the upper bits first.9LB嘉泰姆
R[7:0]: Used to set the PWM duty cycle of the OUTR output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.9LB嘉泰姆
G[7:0]: Used to set the PWM duty cycle of the OUTG output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.9LB嘉泰姆
B[7:0]: Used to set the PWM duty cycle of the OUTB output. All 0 codes are turned off, all 1 codes are the maximum duty cycle, and the 256 level is adjustable.9LB嘉泰姆
4.2.2 Data Receiving and Forwarding9LB嘉泰姆
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S1 is data sent by the Di port of the controller, and S2, S3, and S4 are data forwarded by the cascade CXLE87201.9LB嘉泰姆
Controller Di and Fi2 port data structures: D1D2D3D4... Dn;9LB嘉泰姆
Controller Fi port data structure: DxD1D2D3D4... Dn; where Dx is any 24-bit data bit.9LB嘉泰姆
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The data receiving and forwarding process during chip cascade is as follows: the controller sends data packet D1, chip 1 receives the first set of 24bit, at this time the core9LB嘉泰姆
Chip 1 has no forwarding; Then the controller sends the data packet D2, and chip 1 receives the second set of 24bits, because chip 1 already has the first set.9LB嘉泰姆
24bit, therefore, chip 1 forwards the second set of 24bit to chip 2 through DO, and chip 2 receives the data packet D2 forwarded by chip 1. This9LB嘉泰姆
When chip 2 does not forward; Then the controller sends the data packet D3, and chip 1 forwards the received third group of 24bits to chip 2, because the core9LB嘉泰姆
Chip 2 already stores the second group of 24bits, so chip 2 forwards the third group of 24bits to chip 3, and chip 3 receives the third group9LB嘉泰姆
24bit; and so on, all chips in the cascade will get their own display data. At this time, if the controller sends a Reset signal,9LB嘉泰姆
Some chips will reset and control the output of OUT port after decoding the 24bit data received respectively, completing a data refresh cycle.9LB嘉泰姆
Return to receive ready. Reset is active at low level, the holding time at low level is greater than 200 μs, and the chip is reset.9LB嘉泰姆

5. Typical Application Circuits and Design Recommendations

5.1. Typical application circuit

CXLE87201 typical application circuit is simple, few peripheral components, suitable for compact PCB design. In the 5V system, it is recommended to connect 1KΩ resistors in series on DIN, DO and other signal lines to improve the anti-interference ability. OUT port can directly drive LED lamp beads, maximum withstand voltage 12V, suitable for a variety of RGB LED combination.9LB嘉泰姆

When calculating the refresh rate of the system, if there are 1000 pixels (I .e. 1000 CXLE87201) in the system, the data transmission time of each pixel is 30μs, the overall refresh time is 30ms, and the refresh rate is about 33Hz, which meets most decorative lighting requirements.9LB嘉泰姆

5.2. How to calculate the data refresh rate.9LB嘉泰姆
The data refresh time is calculated based on how many pixels are cascaded in a system, and a set of RGB is usually one pixel (or one9LB嘉泰姆
segment), a CXLE87201 chip can control a set of RGB.9LB嘉泰姆
Calculated according to normal mode:9LB嘉泰姆
1bit data cycle is 1.25 μs (frequency 800KHz), a pixel data including R(8bit), G(8bit), B(8bit)9LB嘉泰姆
A total of 24bit, the transmission time is 1.25μs × 24 = 30μs. If there are 1000 pixels in a system, refresh all the display at once9LB嘉泰姆
The time of is 30μs × 1000=30ms (ignoring Reset signal time), I .e. the refresh rate of one second is: 1 ÷ 30ms & asymp;33Hz.9LB嘉泰姆
The following is a table of the maximum data refresh rate for the number of cascade points:9LB嘉泰姆
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5.3. Constant current curve9LB嘉泰姆
When the CXLE87201 is applied to the design of LED products, the current difference between channels and even between chips is very small, when the load terminal voltage occurs.9LB嘉泰姆
When changing, the stability of its output current is not affected, and the constant current curve is shown in the following figure:9LB嘉泰姆
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6. package and size

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The CXLE87201 provides flip-chip packaging with a size of 470μm × 440 μm and a PAD size of 65 × 65μm, which is suitable for integrated design of wick. The chip substrate needs to be suspended or grounded to ensure heat dissipation and electrical safety.9LB嘉泰姆

7. epilogue

With its high integration, high reliability, flexible cascade control and ultra-low power consumption, the CXLE87201 has become an ideal drive solution in the field of LED decorative lighting. Whether it is in the guardrail tube, point light source, billboard or building facade RGB control, can provide stable, accurate and efficient drive support.9LB嘉泰姆

For more information about CXLE87201 technical information, sample application or purchase information, please visitJTM-IC official websiteGet the latest datasheet and technical support. We are committed to providing customers with high-quality integrated circuit products and solutions to help your lighting design more competitive.9LB嘉泰姆

8.Related Chip Selection GuideMore similar products.....9LB嘉泰姆

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