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CXLE87199 single-wire three-channel LED constant current driver chip depth analysis

In the LED decorative lighting system, the stability, output capability and system expansibility of the driver chip directly affect the overall effect and reliability. As a high-performance single-line three-channel constant current driver chip specially designed for LED decoration products, CXLE87199 has advanced characteristics such as 12mA fixed output current, dual-channel digital interface, 4096-level PWM dimming, etc. It is widely used in guardrail tubes, point light sources, advertising screens, building lighting and other scenes. This paper will give a comprehensive introduction to the chip from the technical characteristics, electrical parameters, application design and other aspects to help developers quickly grasp the key points of its application.QIC嘉泰姆

1. Product Introduction

CXLE87199 is a single-wire three-channel LED constant current driver chip based on power CMOS process. Its biggest highlight is to support DIN and FDIN dual digital input interface, and can automatically switch the input source, with the DO port to achieve signal cascade transmission. Even if a chip failure occurs in the multi-chip cascade system, it will not affect the normal operation of the subsequent chip, which significantly improves the robustness and maintainability of the system.QIC嘉泰姆

The chip integrates MCU single-wire dual-channel digital interface, data latch, three-way LED constant current drive circuit and PWM brightness control module, which is suitable for 5V power supply scheme. The output port has a withstand voltage of 12V, high-precision current output and ultra-low standby power consumption. It is an ideal drive solution for RGB LED lighting applications.QIC嘉泰姆

2. core features

•  High precision constant current output: Each output is fixed at 12mA, suitable for medium power LED lamp beads;QIC嘉泰姆

•  PWM luminance controlSupport 4096 gray level adjustment, can realize smooth color transition and brightness change;QIC嘉泰姆

•  Dual Input and Cascaded Output: Support DIN/FDIN input switching, DO port automatically forward data, the signal is not attenuated;QIC嘉泰姆

•  Ultra-Low Power Standby: Standby current as low as 150 μA, no signal for more than 1 second automatically enter low power mode;QIC嘉泰姆

•  Built-in power-on reset: Ensure that the register is initialized when the chip starts, and the system works stably and reliably;QIC嘉泰姆

•  Wide voltage operating range: Support 4.5V ~ 6.5V power input, typical application is 5V system;QIC嘉泰姆

•  High antistatic abilityHBM mode ESD withstand voltage up to 4000V, adapt to complex industrial environment.QIC嘉泰姆

3. electrical characteristics and operating conditions

The CXLE87199 performs well within the recommended operating voltage range, with a DIN/FDIN input high threshold of 3.5V and a low threshold of 1.0V, providing good noise tolerance. The output constant current of OUT port is 12mA, and the leakage current is lower than 0.5 μA, which ensures that there is no low light in the off state of LED.QIC嘉泰姆

The chip supports 800KHz data transmission rate, the PWM output frequency is 3.6KHz, and the transmission delay time is only 170ns. It responds quickly and is suitable for dynamic display and high-speed refresh scenarios.QIC嘉泰姆

3.1. Limit parametersQIC嘉泰姆
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(1) These levels in the above table, the chip may cause permanent damage to the device and reduce the reliability of the device under long-term use conditions.QIC嘉泰姆
We do not recommend that the chip work beyond these limit parameters under any other conditions;QIC嘉泰姆
(2) All voltage values are tested relative to the system ground.QIC嘉泰姆
3.2. Recommended working conditionsQIC嘉泰姆
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3.3. Electrical characteristicsQIC嘉泰姆
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3.4. Switching characteristicsQIC嘉泰姆
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4. timing control and data protocol

The chip uses a single-wire serial communication protocol, each data cycle is 1.25 μs(800KHz), each chip needs to receive 24-bit RGB data (R, G, B each 8 bits), and supports 256-level PWM dimming. The reset signal (Reset) is active low, and the duration needs to be greater than 200 μs to lock the data and update the output.QIC嘉泰姆

The data frame structure is to continuously send 24-bit data packets of each chip, followed by a reset signal at the end. The chip automatically forwards subsequent data after receiving its own data to achieve cascade control. If no valid data is received for more than 1 second, the chip automatically enters a low-power standby mode, which has a significant energy saving effect.QIC嘉泰姆

4.1. Timing characteristicsQIC嘉泰姆
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(1)0 code or 1 code cycle in 1.25 μs (frequency 800KHz) to 2.5 μs (frequency 400KHz) range, the chip can work normallyQIC嘉泰姆
However, the high level time of 0 code and 1 code must conform to the corresponding numerical range in the above table;QIC嘉泰姆
(2) When reset is not required, the low level time between bytes should not exceed 50μs, otherwise the chip may reset and receive the number again after reset.QIC嘉泰姆
data cannot be transmitted correctly.QIC嘉泰姆
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4.2. Function DescriptionQIC嘉泰姆
        After the chip is powered on and reset, it starts to receive display data. After receiving 24bit, DO port starts to forward the continuous transmission from DIN or FDIN terminal.QIC嘉泰姆
Data to provide display data for the next cascade chip. The DO port is low until the data is forwarded. If DIN or FDIN inputQIC嘉泰姆
Reset reset signal, the chip OUT port will output the PWM waveform of the corresponding duty cycle according to the received 24-bit display data, and the chip will re-QIC嘉泰姆
Waiting to receive new data, after receiving the starting 24bit data, the chip forwards the data through the DO port, and the chip does not receive the Reset messageQIC嘉泰姆
The original output of OUTR, OUTG and OUTB remains unchanged. The chip has a low-power standby mode, if the received 24bit display data fullQIC嘉泰姆
0, the chip enters a low-power standby mode; if the received 24-bit display data is not all 0, the chip enters a normal mode. When the coreQIC嘉泰姆
If the chip does not receive DIN/FDIN display data for more than 1s, the chip will automatically enter low power consumption mode. In low-power mode, the chip is connected.QIC嘉泰姆
Received normal non-all 0 data frames will enter the normal mode for display output.QIC嘉泰姆
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted and attenuated. For all chips cascaded together, the period of data transmissionQIC嘉泰姆
is consistent.QIC嘉泰姆

4.2.1 One frame complete data structureQIC嘉泰姆
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    D1, D2, D3, D4,..., Dn have the same data format, D1 represents the display data packet of the first chip in cascade, Dn represents the first chip in cascadeQIC嘉泰姆
N chip display data packet, each display data packet contains 24bit data bits. Reset represents a reset signal, and the low level is active.QIC嘉泰姆
4.2.2  Data format of DnQIC嘉泰姆
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S1 is data sent by the Di port of the controller, and S2, S3, and S4 are data forwarded by the cascade CXLE87199.QIC嘉泰姆
Controller Di and Fi2 port data structures: D1D2D3D4... Dn;QIC嘉泰姆
Controller Fi port data structure: DxD1D2D3D4... Dn; where Dx is any 24-bit data bit.QIC嘉泰姆
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The data receiving and forwarding process during chip cascade is as follows: the controller sends data packet D1, chip 1 receives the first set of 24bit, at this time the coreQIC嘉泰姆
Chip 1 has no forwarding; Then the controller sends the data packet D2, and chip 1 receives the second set of 24bits, because chip 1 already has the first set.QIC嘉泰姆
24bit, therefore, chip 1 forwards the second set of 24bit to chip 2 through DO, and chip 2 receives the data packet D2 forwarded by chip 1. ThisQIC嘉泰姆
When chip 2 does not forward; Then the controller sends the data packet D3, and chip 1 forwards the received third group of 24bits to chip 2, because the coreQIC嘉泰姆
Chip 2 already stores the second group of 24bits, so chip 2 forwards the third group of 24bits to chip 3, and chip 3 receives the third groupQIC嘉泰姆
24bit; and so on, all chips in the cascade will get their own display data. At this time, if the controller sends a Reset signal,QIC嘉泰姆
Some chips will reset and control the output of OUT port after decoding the 24bit data received respectively, completing a data refresh cycle.QIC嘉泰姆
Return to receive ready. Reset is active at low level, the holding time at low level is greater than 200 μs, and the chip is reset.QIC嘉泰姆

Circuit Design Recommendations for 5. Typical Applications

CXLE87199 typical application circuit is simple, few peripheral components, suitable for compact PCB design. In the 5V system, it is recommended to connect 1KΩ resistors in series on DIN, DO and other signal lines to improve the anti-interference ability. OUT port can directly drive LED lamp beads, maximum withstand voltage 12V, suitable for a variety of RGB LED combination.QIC嘉泰姆

When calculating the refresh rate of the system, if there are 1000 pixels (I .e. 1000 CXLE87199) in the system, the data transmission time of each pixel is 30μs, the overall refresh time is 30ms, and the refresh rate is about 33Hz, which meets most decorative lighting requirements.QIC嘉泰姆

5.1. Typical application circuitQIC嘉泰姆
a) 5V application circuitQIC嘉泰姆

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5.2. How to calculate the data refresh rate.QIC嘉泰姆

The data refresh time is calculated based on how many pixels are cascaded in a system, and a set of RGB is usually one pixel (or oneQIC嘉泰姆
segment), a CXLE87199 chip can control a set of RGB.QIC嘉泰姆
Calculated according to normal mode:QIC嘉泰姆
1bit data cycle is 1.25 μs (frequency 800KHz), a pixel data including R(8bit), G(8bit), B(8bit)QIC嘉泰姆
A total of 24bit, the transmission time is 1.25μs × 24 = 30μs. If there are 1000 pixels in a system, refresh all the display at onceQIC嘉泰姆
The time of is 30μs × 1000=30ms (ignoring Reset signal time), I .e. the refresh rate of one second is: 1 ÷ 30ms & asymp;33Hz.QIC嘉泰姆
The following is a table of the maximum data refresh rate for the number of cascade points:QIC嘉泰姆
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5.3. Constant current curveQIC嘉泰姆

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5.4. Input and output equivalent circuitQIC嘉泰姆
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5.5. Internal structure block diagramQIC嘉泰姆
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6. package and structure size

The CXLE87199 adopts the flip-chip packaging form, the chip size is 470μm × 440 μm, and the PAD size is 65 × 65 μm, which is suitable for the integrated design of the wick. The chip substrate needs to be suspended or grounded to ensure heat dissipation and electrical safety.QIC嘉泰姆

6.1. Chip internal foot bitmap.QIC嘉泰姆
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1. Chip size: 470um * 440umQIC嘉泰姆
2. The thickness of the top aluminum of PAD is 3.6umQIC嘉泰姆
3. Note that the substrate of the chip must be suspended or connected to GNDQIC嘉泰姆
PAD CoordinatesQIC嘉泰姆
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6.2. Inverted schematic diagramQIC嘉泰姆
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7. applicable scenarios

•  RGB point light source, pixel screenQIC嘉泰姆

•  LED guardrail tube, contour light stripQIC嘉泰姆

•  Building facade lighting, curtain wall lightingQIC嘉泰姆

•  Advertising signs, decorative lighting systemQIC嘉泰姆

•  Stage lighting, entertainment lightingQIC嘉泰姆

8. epilogue

With its 12mA high current output, dual-channel input fault tolerance, automatic cascade forwarding and ultra-low power standby, the CXLE87199 performs well in the field of LED decorative lighting. Whether in high-density pixel control systems or long-distance cascade applications, it can provide stable, accurate and efficient drive support.QIC嘉泰姆

For CXLE87199 samples, technical information or application support, welcome to visitJTM-IC official websiteQuery for more information. We are committed to providing global customers with high-quality integrated circuit solutions to help your lighting design more competitive.QIC嘉泰姆

9. Related Chip Selection GuideMore similar products.....QIC嘉泰姆

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