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CXLE87197 high-precision adjustable constant current LED driver chip | 65536 level grayscale | dual channel cascade | JTM-IC

CXLE87197 is a single wire three channel constant current driver chip designed specifically for high-end LED lighting systems. It adopts a wick integrated package and integrates MCU single wire digital interface, data latch, LED constant current driver, and PWM brightness control circuit. The chip supports dual channel input of DIN and FDIN, as well as dual data output of DO1 and DO2, with strong cascading fault tolerance capability. Even if one chip is damaged in the link, it will not affect the normal operation of subsequent chips.

CXLE87197 high-precision adjustable constant current LED driver chip | 65536 level grayscale | dual channel cascade | JTM-IC
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Comprehensive analysis of CXLE87197 high-precision adjustable constant current LED driver chip

          In the field of LED display and decorative lighting, there is an increasing demand for precision, flexibility, and reliability of driving chips. CXLE87197, as a high-performance LED driver chip that integrates adjustable constant current output, 65536 levels of true grayscale, and dual channel level communication, has become an ideal choice for high-end applications such as point light sources, guardrail tubes, indoor and outdoor large screens due to its excellent performance and flexible configuration capabilities. This article will delve into the technical features, control protocol, application design, and system optimization solutions of CXLE87197, providing engineers with a complete reference guide.FmI嘉泰姆


1、 Product Overview

          CXLE87197 is a single wire three channel constant current driver chip designed specifically for high-end LED lighting systems. It adopts a wick integrated package and integrates MCU single wire digital interface, data latch, LED constant current driver, and PWM brightness control circuit. The chip supports dual channel input of DIN and FDIN, as well as dual data output of DO1 and DO2, with strong cascading fault tolerance capability. Even if one chip is damaged in the link, it will not affect the normal operation of subsequent chips.FmI嘉泰姆

          The biggest highlight of this chip is its support for 127 levels of adjustable current ranging from 2mA to 17mA per channel, and its ability to output 65536 levels of true grayscale. Combined with a 1.2MHz high-speed data transmission and dual channel forwarding architecture, it can meet the display and lighting needs of high refresh rates and high grayscale levels.FmI嘉泰姆


2、 Core functional features

•    Wide voltage operating range:3.5V~5.5V, Adapt to various system power supply designs;FmI嘉泰姆

•    Adjustable constant current outputEach channel has a current of 2mA~17mA, adjustable in 127 levels, and the formula is as follows:FmI嘉泰姆
        I(mA) = 2 + 15 × (D - 1) / 126 (D=1~127)
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•    High precision grayscale controlRGB three channels all support 65536 level PWM dimming, with smooth color transitions;FmI嘉泰姆

•    Dual channel input and dual channel outputSupport DIN/FDIN automatic or manual switching, DO1/DO2 dual forwarding, high system reliability;FmI嘉泰姆

•    Ultra high data transmission rate1.2MHz communication frequency, supporting high-density pixel systems;FmI嘉泰姆

•    Low power standby modeStandby current as low as 190μ A, supports automatic and command wake-up;FmI嘉泰姆

•    High precision current outputChannel error≤± 3%, inter chip error; 5%;FmI嘉泰姆

•    Multiple working modesSupports normal mode, DIN mode, FDIN mode, and test mode.FmI嘉泰姆


3、 Electrical characteristics and working conditions

        CXLE87197 performs stably within the recommended operating voltage range, with a DIN/DIN input high-level threshold of 2.8V and a low-level threshold of 1.0V, and has good noise tolerance. The output current of the OUT port can be precisely adjusted within the range of 2mA~17mA, with a leakage current below 0.3A, ensuring that the LED has no low light phenomenon when turned off.FmI嘉泰姆

          The chip supports a data transmission rate of 1.2MHz, with a PWM output frequency of 4kHz and a transmission delay time of only 150ns. It responds quickly and is suitable for high-speed dynamic display scenarios.FmI嘉泰姆

3.1.  Limit parameterFmI嘉泰姆
(1) The levels listed in the table above may cause permanent damage to the device and reduce its reliability when the chip is used for a long time. We do not recommend the chip to operate beyond these limit parameters under any other conditions;FmI嘉泰姆
(2) All voltage values are tested relative to the system ground.FmI嘉泰姆
3.2.    Recommended working conditionsFmI嘉泰姆
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3.3.    Electrical CharacteristicsFmI嘉泰姆
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3.4.    Switch characteristicsFmI嘉泰姆
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3.5.    temporal characteristicFmI嘉泰姆
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(1) The chip can operate normally within the range of 830ns (frequency 1.2MHz) to 2.5us (frequency 400KHz) for 0-code or 1-code cycles, but the high-level time of 0-code and 1-code must comply with the corresponding numerical range in the table above;FmI嘉泰姆
(2) When no reset is required, the low-level time between bytes should not exceed 25us, otherwise the chip may reset and then receive data again, making it impossible to achieve correct data transmission.FmI嘉泰姆
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4、 Control Protocol and Data Format

4.1. Working mode configuration

The chip supports four working modes, configured through a 48 bit command code (first 24 bits command+last 24 bits reverse code):FmI嘉泰姆

•    0xFFFFFF_000000Normal working mode, DIN/FDIN automatic switching;FmI嘉泰姆
        The chip is configured to operate in normal mode. In this mode, the default DIN receives display data for the first time, and the chip detects that there is a signal on the portFmI嘉泰姆
If the number is input, the port will continue to receive data. If no data is received for more than 160ms, it will switch to FDIN to receive data, and the chip will detect itFmI嘉泰姆
If there is a signal input to the port, keep it receiving. If no data is received for more than 160ms, switch back to DIN connectionFmI嘉泰姆
Collect and display data. DIN and FDIN switch in a cyclic manner to receive display data.
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•    0xFFFFFA_000005DIN working mode, only receiving DIN data;FmI嘉泰姆
The chip is configured to work in DIN mode, in which the chip only receives display data input from the DIN end, and the FDIN end data is invalid.
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•    0xFFFFF5_00000AFDIN working mode, only receiving FDIN data;FmI嘉泰姆
The chip is configured to operate in FDIN mode. In this mode, the chip only receives display data input from the FDIN end, and the DIN end data is invalid.
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•    0xFFFFF0_00000FTest mode.FmI嘉泰姆
Chip configured for testing mode
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4.2.      display data

           After the chip is powered on and reset, and receives the mode setting command, it begins to receive the constant current value setting command, and then receives the display data. After receiving 48 bitsFmI嘉泰姆
Afterwards, the DO1 and DO2 ports start forwarding data that continues to be sent from the DIN or FDIN end, providing display data for the next cascaded chip. Forwarding dataFmI嘉泰姆
Previously, the DO1 and DO2 ports were always at a low level. If the DIN or FDIN terminal inputs a Reset signal, the OUT port of the chip will respond based on the received signalFmI嘉泰姆
The 48 bit display data output corresponds to the PWM waveform of the duty cycle, and the chip waits again to receive new data. After receiving the first 48 bitsFmI嘉泰姆
After the data is transmitted through the DO port, the chip maintains the original outputs of R, G, and B unchanged until it receives the Reset signal.FmI嘉泰姆
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted or attenuated. For all cascaded chips, the data transmission cycle isFmI嘉泰姆
coincident.
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4.3. Data frame structure

The complete data frame structure is as follows:FmI嘉泰姆

| C1 | C2 | C3 | D1 | D2 | ... | Dn | Reset |FmI嘉泰姆

•    C1/C2: Mode setting command;FmI嘉泰姆

•    C3Constant current value setting command, 7 bits per channel, a total of 24 bits;FmI嘉泰姆

•    D1~DnPWM setting commands for each chip, 16 bits per channel, for a total of 48 bits;FmI嘉泰姆

•    ResetReset signal, low level effective, duration>80μ s.FmI嘉泰姆
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C1 and C2 are mode setting commands, each containing 24 bits of data. Each chip will receive and forward C1 and C2FmI嘉泰姆
0xFFFFF000000 is the normal working mode command, 0xFFFFA_000005 is the DIN working mode command, and 0xFFFF5_00000A isFmI嘉泰姆
FDIN working mode command, 0XFFFFF0_00000F is the chip test mode command, C3 is the constant current value setting command, and each chip will receive itFmI嘉泰姆
And forward C1, C2, C3.FmI嘉泰姆
D1、D2、D3、D4、… … 、 Dn is the PWM setting command for each chip.FmI嘉泰姆
Reset indicates a reset signal, low level is valid.
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4.4. Constant current and PWM settings

•    C3 commandSet three channel output currents for R [6:0], G [6:0], and B [6:0] respectively, with adjustable 127 levels;FmI嘉泰姆

•    Dn commandSet the three channel PWM duty cycle for R [15:0], G [15:0], and B [15:0] respectively, with adjustable 65536 levels.FmI嘉泰姆
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The C3 command contains 8× 3-bit data bit, high bit first, R7, G7, B7 are fixed to 0.FmI嘉泰姆
R [6:0]: Used to set the constant current value of R output. When R [6:0]=000_0001, it is 2mA, and the full 1 code is 17mA, with adjustable 127 levels.FmI嘉泰姆
G [6:0]: Used to set the constant current value of G output. When G [6:0]=000_0001, it is 2mA, and the full 1 code is 17mA, with adjustable 127 levels.FmI嘉泰姆
B [6:0]: Used to set the constant current value of B output. When B [6:0]=000_0001, it is 2mA, and the full 1 code is 17mA, with adjustable 127 levels.FmI嘉泰姆
(Note that when the current settings of all three channels are all zero codes, it enters low-power mode)
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4.5.      Dn's data formatFmI嘉泰姆

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BIT47… … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … BIT0FmI嘉泰姆
Each PWM setting command contains 16× 3 bits of data, with the higher bits sent first, in the order of RGB.FmI嘉泰姆
R [15:0]: Used to set the PWM duty cycle of R output. All 0 codes indicate shutdown, all 1 code indicates maximum duty cycle, and 65536 levels are adjustable.FmI嘉泰姆
G [15:0]: Used to set the PWM duty cycle of G output. All 0 codes indicate shutdown, all 1 code indicates maximum duty cycle, and 65536 levels are adjustable.FmI嘉泰姆
B [15:0]: Used to set the PWM duty cycle of B output. All 0 codes indicate shutdown, all 1 code indicates maximum duty cycle, and 65536 levels are adjustable.
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4.6.    standby modeFmI嘉泰姆

        Enter standby mode (low-power mode), where no additional commands need to be added, only a complete data frame (C1C2) needs to be sent onceFmI嘉泰姆
Correct) and set C3 to all zeros when writing current. With the reset code, it can enter low-power mode without the need to continuously send standby commands.FmI嘉泰姆
When entering low-power mode, the current of the three channels will be turned off, and the DO output will be at a low level; Exiting standby mode is when sending a complete data frame (C1C2)FmI嘉泰姆
Correct) Set C3 to the normal current mode, and after receiving data from the current level chip, you can exit the low-power mode.
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4.7.      Data reception and forwardingFmI嘉泰姆

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Among them, S1 is the data sent by the Di port of the controller, and S2, S3, S4, and Sn are the data forwarded by the cascaded CXLE87197.FmI嘉泰姆
Controller Di Port Data Structure: C1C2C3D1D2D3D4… … Dn;FmI嘉泰姆
Controller Fi Port Data Structure: C1C2C3DxD1D2D3… … Dn;FmI嘉泰姆
Among them, Dx is any 48 bit data bit, and any one of D1... Dn is a 48 bit display data.FmI嘉泰姆
          The process of chip cascading and data transmission and forwarding is as follows: the controller sends data S1, chip 1 receives C1, C2, and C3 for verification, and ifFmI嘉泰姆
If the command is correct, forward C1, C2, and C3 while absorbing D1. If there is no Reset signal at this time, chip 1 will continue to forward the controllerFmI嘉泰姆
Continue to send data; Chip 2 also receives C1, C2, and C3 for verification. If the command is correct, it forwards C1, C2, and C3 while absorbingFmI嘉泰姆
D2, If there is no Reset signal at this time, chip 2 will continue to forward the data sent by chip 1. And so on, until the controllerFmI嘉泰姆
Send a Reset signal to complete a data refresh cycle, and the chip returns to the receiving preparation state. Reset low level is effective, keep low powerFmI嘉泰姆
If the average time is greater than 80us, the chip will reset. Among them, Dn-0 represents the high 24 bits of Dn, and Dn-1 represents the low 24 bits of Dn.
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5、 Typical Applications and System Design

5.1.    Typical application circuit of dual line cascade, cascade connection method
CXLE87197 supports a dual line cascaded architecture with dual data outputs of DO1 and DO2, enabling the construction of highly reliable cascaded systems. Suggest connecting 100&Omega in series on signal lines such as DIN, FDIN, DO1, DO2, etc; Resistors should be installed, and 100nF decoupling capacitors should be placed between VDD and GND on each chip. The wiring should be as short as possible to ensure signal integrity.
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          To prevent the instantaneous high voltage generated by live plugging and unplugging of the product during testing from causing damage to the input and output pins of the chip signal, it should be addressed in the signal input andFmI嘉泰姆
Output pin connected in series with 100Ω Protect the resistor. In addition, the 104 decoupling capacitors of each chip in the figure are indispensable, and they are wired to the VDD and GND of the chipFmI嘉泰姆
Feet should be as short as possible to achieve the best decoupling effect and stabilize chip operation.

5.2.      Refresh rate calculation

Taking a data rate of 1.2MHz as an example, the transmission time per pixel is 40 μ s. If there are 400 pixels in the system, the overall refresh time is 16ms and the refresh rate is about 62.5Hz, which meets most high dynamic display requirements. The specific correspondence is as follows:FmI嘉泰姆

Pixel count Refresh time (ms) Refresh rate (Hz)
1~400 sixteen sixty-two point five

        The data refresh time is calculated based on how many pixels are cascaded in a system, with a set of RGB typically consisting of one pixel (or segment),FmI嘉泰姆
A CXLE87197 chip can control a set of RGB.FmI嘉泰姆
Calculate according to normal mode:FmI嘉泰姆
The 1-bit data period is 830ns (frequency 1.2MHz), and one pixel data includes R (16 bits), G (16 bits), and B (16 bits)FmI嘉泰姆
48bit, The transmission time is 830ns× 48≈ 40us. If a system has a total of 400 pixels, the time it takes to refresh all displays at onceFmI嘉泰姆
For 40us× 400=16ms (ignoring C1, C2, and Reset signal times), which means a one second refresh rate of 1÷ 16ms=62.5Hz。FmI嘉泰姆
The following is a table of the highest data refresh rate corresponding to cascading points:FmI嘉泰姆
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5.3.    Low power control
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The chip supports instruction and timeout dual-mode standby:FmI嘉泰姆

•    Command standbySet the current values of the three channels in the C3 command to all 0, and the chip enters low-power mode;FmI嘉泰姆

•    Timeout standbyIf no data is received for more than 160ms, it will automatically enter standby mode;FmI嘉泰姆

•    Wake up methodAutomatically wake up upon receiving valid non all 0 data frames.FmI嘉泰姆

5.4      Constant current curveFmI嘉泰姆
        When applying CXLE87197 to LED product design, the current difference between channels and even chips is extremely small. When the load terminal voltage changesFmI嘉泰姆
At this time, the stability of its output current is not affected, and the constant current curve is shown in the following figure:
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5.5.      Internal structure diagramFmI嘉泰姆
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5.6.      Input-output equivalent circuitFmI嘉泰姆

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6、 Packaging and Size

        CXLE87197 adopts a wick integrated package, with a chip size of 400μ m× 555μ m, PAD size of 80× 80μm, Suitable for high integration LED module design. The chip substrate needs to be suspended or grounded to ensure heat dissipation and electrical safety.FmI嘉泰姆

6.1. Pin FunctionFmI嘉泰姆
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6.2.      Internal pin map of chip
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1. Chip size: 400um * 555umFmI嘉泰姆
2. The thickness of the top aluminum layer of PAD is 3.554umFmI嘉泰姆
3. Please note that the substrate of the chip must be suspended or connected to GND
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6.3.      PAD coordinatesFmI嘉泰姆

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7、 Applicable scenarios

•    High density RGB point light source, pixel screenFmI嘉泰姆

•    LED guardrail tube, contour light stripFmI嘉泰姆

•    Indoor and outdoor full-color large screens, billboardsFmI嘉泰姆

•    Building facade lighting and curtain wall lightingFmI嘉泰姆

•    Stage lighting and entertainment lighting systemFmI嘉泰姆


8、 Conclusion

        CXLE87197 demonstrates outstanding comprehensive performance in high-end LED display and decorative lighting fields with its adjustable constant current output, 65536 levels of true grayscale, dual channel cascade architecture, and high-speed communication capability. Whether it is high-precision color reproduction, high refresh rate dynamic display, or high reliability system construction, this chip can provide professional level driving solutions.FmI嘉泰姆

If you need to obtain CXLE87197 samples, technical information or application support, please visitJTM-IC official websiteSearch for more information. We are committed to providing high-quality integrated circuit products and system level technical support to global customers, helping your optoelectronic innovation become more competitive.FmI嘉泰姆


nineTheSelection Guide for Related Chips;                          More similar products ....FmI嘉泰姆

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CXLE8719six 7V three Return to 0 0.73-12mA sixty-five thousand five hundred and thirty-six Core sealing LED decoration driver chip, 16 bit, meteor light Christmas light
CXLE8719seven 7V three Return to 0 2-17mA sixty-five thousand five hundred and thirty-six Core sealing LED decoration driver chip, 16 bit, meteor light Christmas light
CXLE8719eight 12V three Return to 0 12mA four thousand and ninety-six SOP8、 Inverted and integrated wick packaging LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE8719nine 7V three Return to 0 12mA four thousand and ninety-six Inverted and integrated wick LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE87200 7V three Return to 0 2.5mA four thousand and ninety-six Inverted and integrated wick LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE8720one 7V three Return to 0 5mA four thousand and ninety-six Inverted and integrated wick LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE8720two 12V three Return to 0 12mA four thousand and ninety-six SOP8、 Inverted and integrated wick packaging LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE8720three 12V three Return to 0 12mA four thousand and ninety-six SOP8、 Inverted and integrated wick packaging LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE87141A 24V three Returning to 1 18mA two hundred and fifty-six SOP8 LED decoration driver chip, meteor light Christmas light

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