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首页 > Products > Led Driver > Streetlight Spotlight Loghting Desk-lamp Lawn-lamp > CV LED Landscape Lighting Drive >CXLE87189 Single Line Three Channel LED Driver Chip | 65536 Level Brightness | Dual Channel Cascade | JTM-IC
CXLE87189 Single Line Three Channel LED Driver Chip | 65536 Level Brightness | Dual Channel Cascade | JTM-IC

CXLE87189 is a driver chip designed specifically for RGB LEDs, integrating MCU single wire digital interface, data latch, constant current drive, and PWM brightness control circuit. Its biggest feature is supporting dual channel level communication, with DIN and FDIN dual input ports and DO1/DO2 dual output ports, and introducing DENL enable pins, greatly improving the flexibility and reliability of system wiring. Even if a chip is damaged, it does not affect subsequent device communication.

CXLE87189 Single Line Three Channel LED Driver Chip | 65536 Level Brightness | Dual Channel Cascade | JTM-IC
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CXLE87189: Deep Analysis of High Performance Single Line Three Channel LED Driver Chip

        In LED full-color display and decorative lighting systems, efficient, stable, and flexible driver chips are the core for achieving precise color control and system reliability. Launched by JTM-ICCXLE87189It is a highly integrated productSingle line three channel LED constant current driver chip, usingIntegrated wick packaging, possessingDual channel input/outputThe65536 level PWM brightness controlandGamma correctionWith advanced features, it is widely applicable to application scenarios such as point light sources, guardrail tubes, soft light strips, and indoor and outdoor large screens. This article will delve into its technical architecture, communication mechanism, typical applications, and key points of system design.Bve嘉泰姆


1、 Chip Overview and Core Highlights

        CXLE87189 is a driver chip designed specifically for RGB LED, integrated withMCU single line digital interfaceThedata latchTheconstant current driveandPWM brightness controlIntegrated circuit. Its biggest feature is supportDual channel level communication, possessingDIN and FDIN dual input portsandDO1/DO2 dual output outletAnd introduceDENL enable pinThis greatly enhances the flexibility and reliability of system wiring, and even if a chip is damaged, it does not affect subsequent device communication.Bve嘉泰姆

The chip adoptsIntegrated wick packagingThe working voltage range is4.0V~5.5VThe output current of each channel can be2mA~25mAWithin the scope128 levelsAdjustment, PWM brightness level up to65536 level, and built-inGamma 2.4 correctionThe color transition is natural and the display effect is excellent.Bve嘉泰姆


2、 Main technical features

•  High precision constant current outputChannel error≤± 3%, inter chip error; 5%.Bve嘉泰姆

•  Dual channel communication mechanismSupports DIN/FDIN automatic switching or manual specification, with data shaping and forwarding function, and the signal does not attenuate with cascading.Bve嘉泰姆

•  Flexible cascading controlSupport DENL pins to implement matrix based time-sharing control, significantly reducing the number of wiring.Bve嘉泰姆

•  Wide range data rateSupports communication frequencies ranging from 400kHz to 1.2MHz to meet different refresh rate requirements.Bve嘉泰姆

•  Complete protection mechanismBuilt in power on reset, ESD protection and other functions to enhance system reliability.Bve嘉泰姆


3、 Typical Applications and System Design

3.1.    Single line cascading application

CXLE87189 can be accessed through DIN→ DO1 or FDIN→ DO2 implements traditional single line cascading and is suitable for linear layout scenes such as light strips and point light sources. Each chip absorbs its own display data and forwards subsequent data, and the system can achieve overall control without complex wiring.Bve嘉泰姆
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     To prevent the instantaneous high voltage generated by live plugging and unplugging of the product during testing from causing damage to the input and output pins of the chip signal, it should be addressed in the signal input andBve嘉泰姆
Output pin connected in series with 100Ω Protect the resistor. In addition, the 104 decoupling capacitors of each chip in the figure are indispensable, and they are wired to the VDD and GND of the chipBve嘉泰姆
Feet should be as short as possible to achieve the best decoupling effect and stabilize chip operation.
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3.2.    Matrix control (DENL time-sharing mode)

     By using DENL ports and DIN ports, matrix wiring is formed, significantly reducing wiring channels and enabling time-sharing control of multiple light stripsBve嘉泰姆
The DENL of the first chip of each light strip is controlled by the MCU, and the DENL of the subsequent chip is connected to GND. The wiring of each light strip is shown in Figure 7,Bve嘉泰姆
The circuit diagram for the application of multiple light strips is as follows:Bve嘉泰姆
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Detailed explanation of circuit diagram:
The coefficient x represents the number of light strip groups, the coefficient n represents the number of elements in each group, and the coefficient k represents the number of chips per element.Bve嘉泰姆
For example, if x=5, n=10, and k=15, it means there are 5 sets of light strips, each with 10 strips and 15 chips per strip.

In large screen or multi light strip systems, DENL pins can be used to achieve“ Grouping Root” Control structure:Bve嘉泰姆

•    The first chip DENL of each group of light strips is controlled by MCU, and subsequent chips DENL are grounded.Bve嘉泰姆

•    The MCU sequentially lowers the DENLs of each group and synchronously sends corresponding data to achieve time-sharing writing.Bve嘉泰姆

•    After all data is written, send a unified RESET signal to update the output.Bve嘉泰姆

This method can effectively reduce the number of control lines, lower the complexity and cost of the project.Bve嘉泰姆
3.3.  The control process is as follows:
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3.3.1DEN1L pull down, delay t1, the DIN1~DINn data lines of the controller respectively control the 1st~nth light strip of DENL1Bve嘉泰姆
Write data. Data writing completed, delay t2.Bve嘉泰姆
3.3.2DENL2 is pulled down, with a delay of t1. The DIN1~DINn data lines of the controller respectively control the 1st~nth light strip controlled by DENL2Bve嘉泰姆
Write data. Data writing completed, delay t2.Bve嘉泰姆
3.3.3DENL3 is pulled down, with a delay of t1. The DIN1~DINn data lines of the controller control the 1st~nth light strips of DENL3, respectivelyBve嘉泰姆
… …Bve嘉泰姆
Pull up and wait for t4 before entering the next cycle,Bve嘉泰姆
After writing data to all light strips by sequentially lowering DENL, send a reset code to update the data output with a delay of t3Bve嘉泰姆
Attention: After each DENL is lowered and enabled, DIN1~DINn must send data. Even if a certain LED strip does not require updating dataBve嘉泰姆
The same data as the currently held data must be sent.
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3.4.  Write the data sequence diagram as follows:Bve嘉泰姆

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Detailed explanation of timing diagram:Bve嘉泰姆
Data format: The label on the right side of data D represents the number of chips in the light strip;Bve嘉泰姆
For example, D1_1, D1_2, D1_3~D1_k represent the data of the 1st, 2nd, 3rd~k chips of the 1st LED strip.Bve嘉泰姆
D2_1, D2_2, D2_3~D2_k represent the data of the 1st, 2nd, 3rd~k chips of the 2nd LED strip.Bve嘉泰姆
Dn_1, Dn_2, Dn_3~Dn_k represent the data of the 1st, 2nd, 3rd~k chips of the nth LED strip.Bve嘉泰姆
Dxn2, Dxn2, Dxn3~Dxn2~k show the data of the 1st, 2nd, 3rd~k chips of the nxth light strip. If x=10 and n=10, then it meansBve嘉泰姆
The 100th light strip.Bve嘉泰姆
Note:Bve嘉泰姆
t1> 4us,t2> 0us,t1+t2< 20us,t3> 0us,t4> 4us。
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3.5  Input-output equivalent circuitBve嘉泰姆

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4、 Data format and communication protocol

4.1.    Working mode setting

This chip is for single wire dual channel communication and sends signals using reset codes.Bve嘉泰姆
Before receiving display data, the chip needs to configure the correct working mode and select the method of receiving display data. The mode setting command has a total of 48 bits,Bve嘉泰姆
The first 24 bits are the command code, and the last 24 bits are the verification inverse code. The chip reset starts accepting data, and there are four types of mode setting commands as follows,

The chip supports four working modes, which can be set through a 48 bit command code:Bve嘉泰姆

•   0xFFFFFF_000000Automatic Switching Mode (DIN&arr; FDIN)Bve嘉泰姆
        The chip is configured to operate in normal mode. In this mode, the default DIN receives display data for the first time, and the chip detects that there is a signal on the portBve嘉泰姆
If the number is input, the port will continue to receive data. If no data is received for more than 160ms, it will switch to FDIN to receive data, and the chip will detect itBve嘉泰姆
If there is a signal input to the port, keep it receiving. If no data is received for more than 160ms, switch to DIN receiving againBve嘉泰姆
Display data. DIN and FDIN switch in a cyclic manner to receive display data.
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•   0xFFFFFA_000005DIN lock modeBve嘉泰姆
        The chip is configured to work in DIN mode, in which the chip only receives display data input from the DIN end, and the FDIN end data is invalid.
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•   0xFFFFF5_00000AFDIN lock modeBve嘉泰姆

The chip is configured to operate in FDIN mode. In this mode, the chip only receives display data input from the FDIN end, and the DIN end data is invalid.Bve嘉泰姆

•   0xFFFFF0_00000FTest modeBve嘉泰姆

Chip configured for testing modeBve嘉泰姆

4.2.    Constant current value and PWM setting

•   C3 commandSet reference currents for R, G, and B channels (128 levels)Bve嘉泰姆

•   Dn commandSet the PWM duty cycle of R, G, and B channels (256 levels)Bve嘉泰姆
When applying CXLE87189 to LED product design, the current difference between channels and even chips is extremely small. When the load terminal voltage changesBve嘉泰姆
At this time, the stability of its output current is not affected, and the constant current curve is shown in the following figure:Bve嘉泰姆
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4.3.    Data refresh rate calculation

Taking 1.2MHz communication rate as an example:Bve嘉泰姆

•   24 bit transmission time per pixel; 20μsBve嘉泰姆

•   1000 pixel system refresh time& amp; 20ms → Refresh rate& 50HzBve嘉泰姆

The data refresh time is calculated based on how many pixels are cascaded in a system, with a set of RGB typically consisting of one pixel (or segment),Bve嘉泰姆
A CXLE87189 chip can control a set of RGB.Bve嘉泰姆
Calculate according to normal mode:Bve嘉泰姆
The 1-bit data period is 830ns (frequency 1.2MHz), and one pixel data includes 24 bits of R (8-bit), G (8-bit), and B (8-bit),Bve嘉泰姆
The transmission time is 830ns× 24≈ 20μs。 If there are a total of 1000 pixels in a system, the time to refresh all displays at once is 20 secondsBve嘉泰姆
× 1000=20ms (ignoring C1, C2, and Reset signal times), which means a one second refresh rate of 1÷ 20ms=50Hz。Bve嘉泰姆
The following is a table of the highest data refresh rate corresponding to cascading points:Bve嘉泰姆
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4.4.    display dataBve嘉泰姆
        After the chip is powered on and reset, and receives the mode setting command, it begins to receive the constant current value setting command, and then receives the display data. After receiving the 24 bitBve嘉泰姆
Afterwards, the DO1 and DO2 ports start forwarding data that continues to be sent from the DIN or FDIN end, providing display data for the next cascaded chip. Forwarding dataBve嘉泰姆
Previously, the DO1 and DO2 ports were always at a low level. If the DIN or FDIN terminal inputs a Reset signal, the OUT port of the chip will respond based on the received signalBve嘉泰姆
The 24 bit display data output corresponds to the duty cycle of the PWM waveform, and the chip waits again to receive new data. After receiving the 24 bit numberBve嘉泰姆
Afterwards, the data is forwarded through the DO port, and the chip maintains the original outputs of R, G, and B unchanged until it receives the Reset signal.Bve嘉泰姆
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted or attenuated. For all cascaded chips, the data transmission cycle isBve嘉泰姆
coincident.Bve嘉泰姆
4.5.      A complete frame of data structureBve嘉泰姆
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    C1 and C2 are mode setting commands, each containing 24 bits of data. Each chip will receive and forward C1 and C2Bve嘉泰姆
0xFFFFF000000 is the normal working mode command, 0xFFFFA_000005 is the DIN working mode command, and 0xFFFF5_00000A isBve嘉泰姆
FDIN working mode command, 0XFFFFF0_00000F is the chip test mode command, C3 is the constant current value setting command, and each chip will receive itBve嘉泰姆
And forward C1, C2, C3.Bve嘉泰姆
D1、D2、D3、D4、… … 、 Dn is the PWM setting command for each chip.Bve嘉泰姆
Reset indicates a reset signal, low level is valid.Bve嘉泰姆
4.6.    Data format of C3Bve嘉泰姆
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The C3 command contains 8× 3-bit data bit, high bit first, R7, G7, B7 are fixed to 0.Bve嘉泰姆
R [6:0]: Used to set the constant current value of R output. Full 0 code is 2mA, full 1 code is 25mA, adjustable at 128 levels.Bve嘉泰姆
G [6:0]: Used to set the constant current value of G output. Full 0 code is 2mA, full 1 code is 25mA, adjustable at 128 levels.Bve嘉泰姆
B [6:0]: Used to set the constant current value of B output. Full 0 code is 2mA, full 1 code is 25mA, adjustable at 128 levels.
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4.7      Data reception and forwardingBve嘉泰姆
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Among them, S1 is the data sent by the Di port of the controller, and S2, S3, S4, and Sn are the data forwarded by the cascaded CXLE87189.Bve嘉泰姆
Controller Di and Fi2 port data structure: C1C2C3D1D2D3D4… … Dn;Bve嘉泰姆
Controller Fi Port Data Structure: C1C2C3DxD1D2D3… … Dn;Bve嘉泰姆
Among them, Dx is any 24 bit data bit.Bve嘉泰姆
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The process of chip cascading, data transmission, and forwarding is as follows: the controller sends data S1, chip 1 receives C1, C2, and C3 for verification, and ifBve嘉泰姆
If the command is correct, forward C1, C2, and C3 while absorbing D1. If there is no Reset signal at this time, chip 1 will continue to forward the controllerBve嘉泰姆
The data sent; Chip 2 also receives C1, C2, and C3 for verification. If the command is correct, it forwards C1, C2, and C3 while absorbing D2Bve嘉泰姆
If there is no Reset signal at this time, chip 2 will continue to forward the data sent by chip 1. Repeat this process until the controller sends a ResetBve嘉泰姆
Reset signal, complete a data refresh cycle, and the chip returns to the receiving preparation state. Reset low level is effective, maintaining low level for a long timeBve嘉泰姆
At 80&ms, the chip is reset.
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Users can flexibly choose communication frequency based on pixel count, balancing refresh rate and system size.Bve嘉泰姆


5、 Electrical characteristics and parameters

5.1.    Limit parameter

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(1) The levels listed in the table above may cause permanent damage to the device and reduce its reliability when the chip is used for a long time. We do not recommend in itBve嘉泰姆
Under any conditions, the chip operates beyond these limit parameters;Bve嘉泰姆
(2) All voltage values are tested relative to the system ground.
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5.2.      Recommended working conditionsBve嘉泰姆
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5.3.    Electrical CharacteristicsBve嘉泰姆
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5.4.    Switch characteristicsBve嘉泰姆
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5.5.    temporal characteristicBve嘉泰姆
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(1) The chip can operate normally within the range of 830ns (frequency 1.2MHz) to 2.5-ms (frequency 400KHz) for 0-code or 1-code cycles, but 0-code and 1-codeBve嘉泰姆
The high-level time must comply with the corresponding numerical range in the table above;Bve嘉泰姆
(2) When no reset is required, the low-level time between bytes should not exceed 25 seconds, otherwise the chip may reset and then receive data again, making it impossible to achieve dataBve嘉泰姆
Correctly transmitted.Bve嘉泰姆

six、 PCB Design and System Suggestions

•   Signal protectionDIN/FDIN/DO1/DO2: It is recommended to connect 100&Omega in series; Resistors to prevent damage from hot swapping.Bve嘉泰姆

•   Power decouplingA 100nF capacitor should be connected between VDD and GND of each chip, and placed as close to the chip as possible.Bve嘉泰姆

•   Ground wire designEnsure good isolation between power ground (constant current output) and signal ground (logic part).Bve嘉泰姆

•     DENL wiringIn matrix applications, DENL control lines should be kept away from high-frequency signals to avoid false triggering.Bve嘉泰姆


7、 Packaging and size

7.1.    Internal pin map of chip

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1. Chip size: 400um * 600umBve嘉泰姆
2. The thickness of the top aluminum layer of PAD is 3.554umBve嘉泰姆
3. Please note that the substrate of the chip must be suspended or connected to GND
7.2.    PAD coordinates
7.3.      Pin function

8、 Conclusion

      CXLE87189 is known for itsSingle line controlTheDual channel redundancyTheHigh precision outputandFlexible matrix control capabilityBecoming an ideal choice in the field of LED full-color display and decorative lighting. Whether it's a simple LED strip project or a complex large screen system, this chip can provide stable, efficient, and highly consistent driving solutions.Bve嘉泰姆

For more technical information, sample application or design support, please visit the official website of Jiataimu:jtm-ic.comWe are committed to providing professional product services and system level technical support to our customers.Bve嘉泰姆


9Selection Guide for Related Chips;                          More similar products ....Bve嘉泰姆

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model Port withstand voltage number of channels communication protocol Single channel current Gray level package form remark
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DMX512
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CXLE8720three 12V three Return to 0 12mA four thousand and ninety-six SOP8、 Inverted and integrated wick packaging LED decoration driver chip, low-power mode, meteor light Christmas light
CXLE87141A 24V three Returning to 1 18mA two hundred and fifty-six SOP8 LED decoration driver chip, meteor light Christmas light

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