The CXLE87205 is manufactured using power CMOS technology and integrates MCU firmware, single wire digital interface, data latch, and three LED constant current driver circuits internally. Its VDD pin is equipped with a built-in 5V voltage regulator, supporting a wide voltage input range of 6-24V. The peripheral circuit is simple, greatly reducing system design and material costs
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[ CXLE87205 ]"
CXLE87205 Three Channel LED Constant Current Driver IC: Technical Explanation and Application Guide
In the field of LED decorative lighting, the performance of constant current driver ICs directly determines the stability and display effect of the entire lighting system. CXLE87205, as a three channel LED fixed 18mA constant current driver chip with integrated internal control synchronization function, is widely used in scenarios such as guardrail tubes, point light sources, LED light strips, etc. It has the advantages of high integration, high reliability, and easy scalability. This article will provide an in-depth analysis of the functional characteristics, electrical parameters, typical circuit design, and system application recommendations of CXLE87205, to help engineers better understand and apply the chip.
1、 Chip Overview and Core Features
The CXLE87205 is manufactured using power CMOS technology and integrates MCU firmware, single wire digital interface, data latch, and three LED constant current driver circuits internally. Its VDD pin is equipped with a built-in 5V voltage regulator, supporting a wide voltage input range of 6-24V. The peripheral circuit is simple, greatly reducing system design and material costs.
This chip has the following outstanding features:
• Three 18mA constant current outputsEach output current has high accuracy, and the inter channel error does not exceed± 3%, with inter chip error not exceeding± 5%.
• 256 level PWM dimmingSupport fine brightness adjustment to meet the visual needs of various scenes.
• Single line serial cascade interfaceSupport automatic shaping and forwarding, signal transmission does not attenuate with increasing cascade distance.
• Dual mode of internal/external controlIn external control mode, the data transmission rate reaches 800KHz. In internal control mode, it supports 2048 point data transmission and can achieve automatic switching of colorful patterns.
• High voltage resistance and low power consumptionThe OUT port has a withstand voltage of 24V and a typical static current value of 1.65mA, with excellent power consumption control.
2、 Pin function and internal structure
CXLE87205 adopts SOP8 packaging, and the pin definitions are as follows:
• OUTR/OUTG/OUTB: Three channels of N-channel open drain constant current output
• DIN: Serial Data Input
• DO: Data output, used for cascading
• VDD: Positive pole of power supply (built-in 5V voltage regulator)
• GND: Power Ground
• NC: Empty feet
The structure includes OSC oscillator, serial decoding module, internal control module, data shaping and forwarding unit, and constant current drive circuit, ensuring efficient synchronization of signal reception, decoding, and output. Its internal
2.1. Internal structure diagram
3、 Electrical characteristics and working conditions
Within the recommended working voltage range of 4.5V~6.5V, CXLE87205 exhibits excellent electrical performance:
• The typical value of constant current output is 18mA, which can work stably in an environment from -40 ℃ to+85 ℃.
• The leakage current of the output port is less than 0.5 μ A, and it consumes almost no power in the off state.
• The data transmission rate supports 800KHz (external control) and 500KHz (internal control), with a PWM output frequency of 666Hz.
The chip has a comprehensive protection mechanism, including ESD protection (HBM 3000V) and power on reset function, ensuring reliable operation in harsh environments.
3.1. Limit parameter
(1) The levels listed in the table above may cause permanent damage to the device and reduce its reliability when the chip is used for a long time. We do not recommend the chip to operate beyond these limit parameters under any other conditions;
(2) All voltage values are tested relative to the system ground.
3.2 Recommended working conditions
3.3. Electrical Characteristics
3.4. Switch characteristics
3.5 temporal characteristic
(1) The chip can operate normally within the range of 1.25 μ s (frequency 800KHz) to 2.5 μ s (frequency 400KHz) for 0 or 1 code cycles, but the high-level time of 0 and 1 codes must comply with the corresponding numerical range in the table above;
(2) When no reset is required, the low-level time between bytes should not exceed 50 seconds, otherwise the chip may reset and then receive data again, making it impossible to achieve correct data transmission.
4、 Data transmission and cascading system
CXLE87205 adopts a single line zeroing code communication protocol, where each pixel corresponds to 24 bits of data (8 bits for R/G/B), with the higher bits sent first. After the controller sends the data frame, each chip receives and forwards the data in sequence, and finally sends a Reset signal (low level>200μ); s) Unified update output.
When cascading, the chip has the capability to; Automatic shaping and forwarding; Function to ensure that the signal is not distorted during long-distance transmission. The system refresh rate is related to the number of pixels, for example, when cascading 1000 chips, the refresh rate can still reach 33Hz, which meets most dynamic display requirements.
This chip is for single line communication and sends signals using reset codes. After the chip is powered on and reset, it receives data from the DIN end. After receiving 24 bits, the DO port starts forwarding the data that continues to be sent from the DIN end, providing input data for the next cascaded chip. Before forwarding data, the DO port remains at a low level. If the DIN terminal inputs a Reset signal, the OUT port of the chip will output a PWM waveform with a corresponding duty cycle based on the received 24 bit data, and the chip will wait again to receive new data. After receiving the starting 24 bit data, the data will be forwarded through the DO port. Before receiving the Reset signal, the original outputs of OUTR, OUTG, and OUTB of the chip will remain unchanged.
The chip adopts automatic shaping and forwarding technology, and the signal will not be distorted or attenuated. For all chips cascaded together, the data transmission cycle is consistent.
4.1. A complete frame of data structure
D1、D2、D3、D4、… … 、 The Dn data format is the same, where D1 represents the data packet of the first chip in cascade, and Dn represents the data packet of the nth chip in cascade, with each packet containing 24 data bits. Reset indicates a reset signal, low level is valid.
4.2 Data format of Dn
Each data packet contains 8× 3 bits of data, high bits are sent first.
R [7:0]: Used to set the PWM duty cycle of the OUTR output. All 0 codes indicate shutdown, all 1 code indicates maximum duty cycle, adjustable in 256 levels.
G [7:0]: Used to set the PWM duty cycle of OUTG output. All 0 codes indicate shutdown, all 1 code indicates maximum duty cycle, adjustable in 256 levels.
B [7:0]: Used to set the PWM duty cycle of OUTB output. All 0 codes indicate shutdown, all 1 code indicates maximum duty cycle, adjustable in 256 levels.
4.3 Data reception and forwarding
Among them, S1 is the data sent by the controller, and S2, S3, and S4 are the data forwarded by the cascaded CXLE87205.
The data reception and forwarding process during chip cascading is as follows: the controller sends data packet D1, chip 1 receives the first set of 24 bits, and at this time chip 1 does not forward; Then the controller sends data packet D2, and chip 1 receives the second set of 24 bits. Since chip 1 already has the first set of 24 bits, chip 1 forwards the second set of 24 bits to chip 2 through DO. Chip 2 receives the data packet D2 forwarded by chip 1, and at this time, chip 2 does not forward it; Then the controller sends data packet D3, and chip 1 forwards the received third set of 24 bits to chip 2. Since chip 2 already has the second set of 24 bits, chip 2 forwards the third set of 24 bits to chip 3, which receives the third set of 24 bits; Similarly, all cascaded chips will receive their respective display data. At this point, if the controller sends a Reset signal, all chips will reset and decode the 24 bit data they receive to control the OUT port output, completing a data refresh cycle, and the chips will return to the receiving preparation state. Reset low level is effective. If the low level is maintained for more than 200 seconds, the chip will reset. However, it should be noted that the low level time should not exceed 20000 seconds, otherwise the chip may switch to internal control mode.
5、 Typical Application Circuit Design
5.1. Basic wiring diagram
To prevent the instantaneous high voltage generated by live plugging and unplugging of the product during testing from causing damage to the chip signal input and output pins, 100&Omega should be connected in series between the signal input and output pins; Protect the resistor. In addition, the 104 decoupling capacitors of each chip in the figure are indispensable, and the VDD and GND pins of the wiring to the chip should be as short as possible to achieve the best decoupling effect and stabilize the chip operation.
A 0.1 μ F decoupling capacitor should be connected between VDD and GND of each chip, and it is recommended to connect the DIN and DO signal lines in series with 100 Ω; Resistors are used to protect against ESD and plug-in shocks. When the power supply voltage is higher than 5V, a current limiting resistor needs to be connected in series before VDD, for example:
• 6V → 50Ω
• 12V → 650Ω
• 24V → 1.8KΩ
5.2. Constant current configuration and expansion scheme
To ensure that the OUT port operates in the optimal constant current state (1.2V~3V), a resistor can be connected in series at the output end to adjust the voltage. For example, driving 6 series connected LEDs (each with a voltage drop of 2V) in a 24V system, it can be calculated that approximately 583Ω Resistance.
If a larger driving current is required, the OUTR/OUTG/OUTB channels can be short circuited for use, with a maximum constant current value of 54mA. The software needs to control three sets of PWM registers simultaneously to achieve precise current superposition.
CXLE87205 can be configured for DC6-24V voltage supply, but different power resistors should be configured based on the input voltage. Resistance calculation is required
Method: The VDD port current is calculated at 10mA, and the VDD series resistance R=(DC-5.5V)÷ 10mA (DC is the power supply voltage).
The list of typical values for configuring resistors is as follows:
5.3. Internal control mode and automatic switching
When the DIN signal is lost for more than 300ms, the chip automatically switches to internal control mode, cyclically executes 7 preset RGB states (such as red, green, blue, yellow, purple, etc.), and synchronously controls the lower level chips through the DO port, achieving a fully internal control light strip effect without the need for a controller.
When the chip power supply is normal and no signal input to DIN is detected, or when the signal was originally normal but suddenly lost for about 300ms, the chip
The chip enters the internal control mode and performs the following cyclic flashing:
Note:‘ 1’ Indicates channel shutdown,‘ 0’ Indicates that the channel is open.
As shown in the figure below, when chip 1 detects no signal input after power on, it enters the internal control mode, and the RGB performs internal control pattern changes. At the same time, the DO port will automatically send data to the subsequent chip to achieve synchronous display function.
After entering the internal control mode, the chip sends 2048 data points.
5.4. How to Calculate Data Refresh Rate
The data refresh time is calculated based on how many pixels are cascaded in a system. A set of RGB is usually one pixel (or segment), and a CXLE87205 chip can control a set of RGB.
Calculate according to normal mode:
The 1-bit data cycle is 1.25μ s (frequency 800KHz), and one pixel data includes 24 bits of R (8-bit), G (8-bit), and B (8-bit), with a transmission time of 1.25μ s× 24=30μs。 If there are a total of 1000 pixels in a system, when refreshing all displays at once
Between 30μ s× 1000=30ms (ignoring Reset signal time), which means a one second refresh rate of 1÷ 30ms≈ 33Hz。
The following is a table of the highest data refresh rate corresponding to cascading points:
5.5. How to make CXLE87205 work in the optimal constant current state
CXLE87205 is a constant current drive. According to the constant current curve, when the OUT port voltage reaches 0.8V, it will enter a constant current state. But the higher the voltage, the better. The higher the voltage, the greater the power consumption of the chip, and the more severe the heating, which reduces the reliability of the entire system. It is recommended that the voltage between 1.2 and 3V be appropriate when the OUT port is turned on, and the excessive voltage of the OUT port can be reduced by connecting resistors in series. The following is the calculation method for selecting resistance values:
System driving voltage: DC
Single LED conduction voltage drop: Vled
Number of LEDs in series: n
Constant current value: Iout
Constant current voltage: 1.5V
Resistance: R
R=（DC-1.5V -Vled×n）÷ Iout
Example: System power supply: DC24V, single LED conduction voltage drop: 2V, number of LEDs in series: 6, constant current value: 18mA. According to the above formula, R=(24V-1.5V-2V× 6)÷ 18 mA≈ 583Ω Simply connect 583Ω in series with the OUT port; The resistors on both sides are sufficient. In practical applications, when the light bar is long and far from the power supply point, VCC will decrease. If the voltage at the R/G/B ports does not reach the constant current inflection point voltage, the output may not reach the rated constant current value. In this case, the constant current voltage value can be increased, such as to 3V, to reduce the impact on the lights, or the power supply point can be added in engineering to ensure that the decrease in power supply voltage is small.
5.6. Constant current curve
When applying CXLE87205 to LED product design, the current difference between channels and even chips is extremely small. When the load terminal voltage changes, the stability of its output current is not affected. The constant current curve is shown in the following figure:
6、 System optimization and engineering recommendations
• Wiring optimizationTry to keep the decoupling capacitor as close as possible to the VDD-GND pin of the chip, and keep the signal line away from high-frequency interference sources.
• power managementLong light strips should be connected to power sources at multiple locations to avoid voltage drops at the end that may affect constant current accuracy.
• thermal designThe output port voltage should not be too high, and a series resistor should be reasonably selected to control the temperature rise of the chip.
7、 Conclusion
CXLE87205, with its high integration, precise current control, flexible cascading capability, and dual-mode operation, has become an ideal driving solution in the field of LED decorative lighting. Whether in guardrail tubes, point light sources, or customized LED display projects, this chip can provide a stable, efficient, and easy-to-use control foundation.
For more technical information, sample requests, or procurement information about CXLE87205, please visitJTM-IC official websiteWe are committed to providing customers with complete IC solutions and technical support to help your lighting design become more competitive.
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