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首页 > Products > Led Driver > Streetlight Spotlight Loghting Desk-lamp Lawn-lamp > CV LED Landscape Lighting Drive >CXLE87133BCE DMX512 Differential Parallel LED Driver IC Data Manual | 16 Bit Grayscale Gamma Correction | JTM-IC Official Solution
CXLE87133BCE DMX512 Differential Parallel LED Driver IC Data Manual | 16 Bit Grayscale Gamma Correction | JTM-IC Official Solution

CXLE87133BCE is a 3-channel LED constant current driver chip based on differential parallel architecture, supporting up to 4096 channel addressing and built-in E2PROM storage unit, which can achieve address encoding and configuration saving without external memory. The chip adopts enhanced gamma correction technology to convert 8-bit input grayscale into 16 bit output, significantly improving visual smoothness and color hierarchy.

CXLE87133BCE DMX512 Differential Parallel LED Driver IC Data Manual | 16 Bit Grayscale Gamma Correction | JTM-IC Official Solution
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CXLE87133BCE DMX512 Differential Parallel LED Driver Chip: A New Standard for Professional Lighting Control1gQ嘉泰姆

          In professional LED lighting and control systems, the DMX512 protocol has become the industry mainstream due to its stability, reliability, and strong scalability. CXLE87133BCE, as a high-performance and highly integrated DMX512 differential parallel protocol LED driver chip, is not only fully compatible with the DMX512 (1990) standard, but also has enhanced functions such as 16 bit grayscale output, 2.2 gamma correction, and adaptive decoding. It is widely used in high-end scenes such as stage lighting, building facade lighting, and landscape lighting. This article will deeply analyze the technical characteristics, electrical parameters, system design points, and practical application suggestions of the chip.1gQ嘉泰姆


1、 Overview and Technical Positioning of Chips

      CXLE87133BCE is a 3-channel LED constant current driver chip based on differential parallel architecture, supporting up to 4096 channel addressing and built-in E2PROM storage unit, which can achieve address encoding and configuration saving without external memory. The chip adopts enhanced gamma correction technology to convert 8-bit input grayscale into 16 bit output, significantly improving visual smoothness and color hierarchy.1gQ嘉泰姆

It has a capacity of 200Kbps– The 1000Kbps adaptive decoding capability can recognize and process a wide range of DMX512 signal rates, greatly improving system compatibility and stability. In addition, the chip supports online code writing and breakpoint discrimination functions, greatly simplifying on-site installation and post maintenance processes.1gQ嘉泰姆


2、 Core functional features

•     Compatible with the complete DMX512 protocolSupports standard and extended DMX512 signals, with strong anti-interference capabilities for differential inputs.1gQ嘉泰姆

•     16 bit grayscale+gamma correction 2.2Output 65536 levels of grayscale, which is more in line with the human visual response curve.1gQ嘉泰姆

•     3-channel high-precision constant current output: Current per channel 3– 80mA adjustable, channel/chip error; 3%.1gQ嘉泰姆

•     Built in E2PROM and online code writingSupports AB line code writing, dual backup of addresses, and partial damage does not affect reading.1gQ嘉泰姆

•     High refresh rate and high load capacityThe refresh rate of the screen can reach 2kHz and supports up to 4096 channels.1gQ嘉泰姆

•     Wide voltage adaptation and high voltage resistanceOUT port withstand voltage 30V, supports multi lamp series design.1gQ嘉泰姆

•     Industrial grade reliabilityWorking temperature: -40 ℃~+85 ℃, ESD anti-static up to 4000V.1gQ嘉泰姆


3、 Pin definition and internal structure

CXLE87133BCE adopts SSOP10 packaging, with clear pin definitions:1gQ嘉泰姆

 
pin name Functional Description
one GND power ground
2– four OUTR/G/B PWM constant current output
five REXT External resistor setting current
six ADRO Address coding output
seven ADRI Address coding input (built-in pull-up)
eight AI Positive end of differential signal
nine BI Negative terminal of differential signal
ten VDD Positive pole of power supply (3.8V– 6V)

The chip integrates OSC oscillator, DMX512 decoding module, E2PROM controller, gamma correction unit, and three constant current drive circuits internally, with complete signal reception, processing, and output capabilities.1gQ嘉泰姆


4、 Key electrical parameters and working conditions

4.1    Extreme working conditions:

•    Power supply voltage VDD: -0.5V~+6.5V1gQ嘉泰姆

•    Output port withstand voltage Vout: 30V1gQ嘉泰姆

•    Working temperature: -40 ℃~+85 ℃1gQ嘉泰姆

•    ESD anti-static: 4000V (HBM)1gQ嘉泰姆
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(1) Long term operation of chips under the above extreme parameter conditions may result in reduced device reliability or permanent damage, and is not recommended for practical use1gQ嘉泰姆
When used, any parameter reaches or exceeds these limit values.1gQ嘉泰姆
(2) All voltage values are tested relative to the system ground.
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4.2    Recommended working conditions:

•    Power supply voltage: 3.8V~6V (typical 5V)1gQ嘉泰姆

•    Output current range: 3mA~80mA/channel1gQ嘉泰姆

•    Data transmission rate: 200Kbps~1000Kbps adaptive1gQ嘉泰姆

The typical dynamic current of the chip under 5V power supply is 4mA, which has excellent power consumption control and thermal management capabilities.1gQ嘉泰姆

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4.3    Electrical Characteristics1gQ嘉泰姆

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4.4    Switch characteristics1gQ嘉泰姆

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5、 System Design and Configuration Guide

5.1. Constant current value setting

The output current is determined by the resistance of the REXT pin to ground, and the formula is as follows:1gQ嘉泰姆

Iout​=​48​/(400+Rext)

For example:1gQ嘉泰姆

•    Output 20mA→ Rext ≈ 2000Ω1gQ嘉泰姆

•    Output 60mA→ Rext ≈ 400Ω1gQ嘉泰姆

      OUTR, OUTG, and OUTB are constant current outputs with a maximum current of 80mA. It is not recommended to set the current to a higher value for application. Constant current1gQ嘉泰姆
The current formula is determined by the resistance of REXT to ground:1gQ嘉泰姆
Iout=48/(400+Rext) (1)1gQ嘉泰姆
Rext=(48/Iout)-400 (2)1gQ嘉泰姆
Rext is the resistance across the REXT pin and ground, measured inΩ , Iout is the current output from the OUTR, OUTG, and OUTB ports.
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5.2. Code writing and address recognition

The chip supports AB line online code writing. After the code writing is completed:1gQ嘉泰姆

•    The first address chip lights up red1gQ嘉泰姆

•    The remaining address chips are illuminated with white lights1gQ嘉泰姆
Easy to quickly identify and locate breakpoints on site.
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5.3. Design of Power Supply and Protection Circuit

At different system voltages, it is recommended to configure the following (typical values):1gQ嘉泰姆

VCC
Rz (Ω)
Rf / Ro (Ω)
RA / RB (Ω)
24V
2K– 2.4K
300– four hundred
3K– 5K
12V
750– eight hundred and twenty
300– four hundred
3K– 5K
5V
eighty-two
3K– 5K

Notes:1gQ嘉泰姆

•    It is recommended to use shielded twisted pair cables for AI/BI bus, with the end connected to 120Ω Match resistance.1gQ嘉泰姆

•    The controller and each chip must be grounded together to prevent common mode voltage from damaging the device.1gQ嘉泰姆

•    VDD and GND must be connected with a voltage of 0.1 μ m; F decoupling capacitor, it is recommended to use capacitors above 105 (1μ F) for high current output.1gQ嘉泰姆

5.4    Constant current curve:1gQ嘉泰姆

CXLE87133BCE has excellent constant current characteristics, with minimal current differences between channels and even chips.1gQ嘉泰姆
(1) Current error between channels± 3 ℅, and the current error between chips± 3%.1gQ嘉泰姆
(2) When the voltage at the load end changes, the output current of CXLE87133BCE is not affected, as shown in the following figure.1gQ嘉泰姆
(3) As shown in the following figure, the relationship between the current I at the CXLE87133BCE output port and the voltage Vds curve applied to the port indicates that the smaller the current I, the more constant the current is1gQ嘉泰姆
The smaller the Vds required in the state.
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6、 Gamma correction and grayscale enhancement

6.1 Enhanced Gamma Correction 2.2 Explanation:
6.1.1 CXLE87133BCE has built-in gamma correction with a coefficient of 2.2, which corrects 256 levels of grayscale to 65536 levels of grayscale.1gQ嘉泰姆
6.1.2 CXLE87133BCE adopts an enhanced design approach, with RGB output turn-on time being: base turn-on time+corrected grayscale time. On the basis of each level of grayscale time, a basic turn-on time is added to compensate for the actual turn-on delay and the significant difference in turn-on time between different high-power constant current drive ICs in high-power applications, to ensure that in most cases, the first level of grayscale can be clearly perceived by the human eye when combined with different high-power constant current ICs.1gQ嘉泰姆
6.1.3. Positive polarity: The basic activation time is about 85ns.

        The CXLE87133BCE has a built-in 2.2 coefficient gamma correction module that maps 256 levels of input grayscale to 65536 levels of output, and adds a basic turn-on time of approximately 85ns to compensate for the response delay of high-power driver ICs, ensuring excellent visual performance even at low grayscale.1gQ嘉泰姆

6.2. Communication Data Protocol:1gQ嘉泰姆

CXLE87133BCE data reception is compatible with standard DMX512 (1990) protocol and extended DMX512 protocol, with adaptive decoding for transmission rates ranging from 200Kbps to 1000Kbps. The protocol waveform is shown below: the chip is a differential input of AI and BI, and the timing waveform of AI is shown in the figure. BI is opposite to AI.1gQ嘉泰姆

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Note 1: The field consists of 11 bits, including a 0 start bit, 8 data bits, and 2 stop bits. The 0 starting bit is a low level and the stop bit is a stop bit1gQ嘉泰姆
If it is a high level and the data in the data bit is 0, then the corresponding time period is a low level; If the data is 1, then the corresponding time period is high level. 01gQ嘉泰姆
The duration of the start, stop, and data bits must be the same.
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6.3.  IC receiving instructions:1gQ嘉泰姆

1.     When a reset signal appears on the AI and BI lines, the IC enters the receiving preparation state. The address counter clears to 0.1gQ嘉泰姆
2.     The first field in the data packet is the starting field, and its 8-bit data must be“ 0000_0000” This field is not used as display data.1gQ嘉泰姆
The valid fields used for display start from the second field, and the second field of the DMX512 packet is the first field of the valid data. IC adaptive1gQ嘉泰姆
The data transmission rate is between 200Kbps and 1000Kbps. The duration of fields corresponding to different rates varies, but regardless of the transmission frequency1gQ嘉泰姆
200Kbps/400Kbps/1000Kbps, Just make sure that the duration of all valid fields is the same as the duration of the starting field.1gQ嘉泰姆
When the IC receives data, the interval between two reset signals should not be less than 4ms, and even in the case of very few parallel points, the frame rate should not be greater than1gQ嘉泰姆
250Hz。
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6.4.    Precautions for Controller Data Transmission:1gQ嘉泰姆

For the standard DMX512 (1990) protocol, if one port of the controller is connected to 512 channels, which is 170 pixels,1gQ嘉泰姆
To achieve a refresh rate of 30Hz, the time width of each frame is 33.33ms, and the transmission time of 1-bit is 4&ms, then the effective data time width is1gQ嘉泰姆
If 88+4μ s * 11bit * 512=22.7ms, then the time interval between each frame of data is 33.33-22.7=  10.63ms. At this time1gQ嘉泰姆
The data line remains at a high level within the interval until the next reset signal.1gQ嘉泰姆
2. CXLE87133 requires that the reset signal interval for each data packet of the controller should not be less than 4ms, that is, the maximum frame rate should not exceed 250Hz,1gQ嘉泰姆
Otherwise, the screen may not display properly.
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6.5.  Notes on coding:1gQ嘉泰姆

1.     After completing the code writing process, the IC driver for the first address code will keep the red light on, while the other address IC drivers will keep the white light on. The newly written address code1gQ嘉泰姆
Effective, can be used for breakpoint discrimination.1gQ嘉泰姆
2.     After completing the code writing, do not remove the AB line first. Use the dedicated testing program provided by the code writer to test and confirm whether the code writing is complete1gQ嘉泰姆
All right.1gQ嘉泰姆
3.     The address input terminal line on the AI and BI ports of the code writer should be unplugged from the code writer after the code writing is completed to avoid accidental writing when the code writer malfunctions1gQ嘉泰姆
The code. After pulling out the coding line, it can be suspended and wrapped with insulating tape, without the need for special grounding.
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6.6. Precautions for differential bus connection:1gQ嘉泰姆

1.     The controller and IC, as well as between ICs, must be grounded together to prevent excessive common mode voltage from breaking down the IC. A shielding layer can be used as a common ground wire1gQ嘉泰姆
Reliable connection of multiple IC nodes and reliable grounding at one point, without double or multi terminal grounding.1gQ嘉泰姆
2.     The protective resistors connected in series between the AI and BI lines on the board and the IC must be consistent, and the routing of the AIBI line from the solder pad to the IC on the board should be as good as possible1gQ嘉泰姆
agreement.1gQ嘉泰姆
3.     AI and BI buses should use shielded twisted pair cables as much as possible (especially in projects where strong and weak current cable trays are shared, near transmission towers, or when lightning strikes are common)1gQ嘉泰姆
Multiple areas) to reduce interference and lightning strikes. Use ordinary Category 5e shielded twisted pair cables, but pay attention to purchasing copper wires.1gQ嘉泰姆
4.     In the 485 bus, the distance between the 485 nodes and the backbone should be minimized as much as possible. It is generally recommended to use a hand-in-hand bus topology for the 485 bus1gQ嘉泰姆
Structure. The star shaped structure will generate reflected signals, affecting the quality of 485 communication. If it is necessary to require the 485 node to be separated from the 485 bus during the construction process1gQ嘉泰姆
If the distance between the backbone exceeds 1m, it is recommended to use a 485 repeater to make a fork of the 485 bus. If it is required during the construction process to1gQ嘉泰姆
When using a star topology structure, a 485 hub should be used.1gQ嘉泰姆
5.     As the transmission distance of 485 bus increases, echo reflection signals will be generated. If the transmission distance of 485 bus is long, it is recommended to implement1gQ嘉泰姆
Connect a 120 ohm terminal matching resistor in parallel to the AI and BI lines at the 485 communication end.
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7、 Typical application scenarios

•    Stage lighting systemSupports high refresh rate and precise color control, with no flicker.1gQ嘉泰姆

•    Strip lights on the exterior facade of buildingsMulti chip cascading to achieve overall linkage effect.1gQ嘉泰姆

•    Landscape Lighting and Media Wall16 bit grayscale brings smooth gradients and transitions.1gQ嘉泰姆

•    Indoor decorative lightingWall washers, point lights, and line lights are all suitable.1gQ嘉泰姆


8、 Design considerations

•    Frame rate controlThe reset interval between DMX512 packets should not be less than 4ms, and the frame rate should not exceed 250Hz.1gQ嘉泰姆

•    power consumption managementIt is recommended to control the output port voltage at 0.8V; Between 3.87V, avoid overheating of the chip.1gQ嘉泰姆

•    topological structureSuggest using '; Hand in hand; The bus structure and star structure need to be used in conjunction with 485 relays or hubs.1gQ嘉泰姆


9、 Application Information

 

9.1.    Application image: RGB; 3-color application

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Note: 1. When using the A and B line coding method, the encoder/controller does not need to be connected to the ADRI of the first IC during coding.1gQ嘉泰姆
2. Pay attention to the selection of voltage divider resistor R1 to avoid excessive power consumption of the IC.1gQ嘉泰姆
3.   The REXT port must have a resistor connected to ground to set the output current, and this port cannot be suspended.1gQ嘉泰姆
4.   The 104 capacitor of VCC to ground is the recommended value when the channel current is set to 20mA. If a larger channel current is set, the capacitor value should be increased,1gQ嘉泰姆
For example, if the channel current is set to 40mA, it is recommended to use a capacitance value of 105 or higher.
9.2. Component Selection Table 1 (Non transistor Applications)
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(1) Selection of Value for Lamp String Resistance R11gQ嘉泰姆
Due to the recommended long-term power consumption of the package not exceeding 400mW, the IC power consumption should be set to be less than 400mW. As the driving current increases,1gQ嘉泰姆
The output voltage Vout of the chip channel should be reduced, i.e. 400mW>; 5.2V * 10mA+Vout * Iout * N (where N is the number of channels, Vout is the channel port voltage, and Iout is the channel set current), when N=3 and Iout=30mA, Vout<; 3.87V, Also, because Voucher=VCC-M * VL-R1 * Iout (where M is the number of lamps connected in series on a single channel and VL is the voltage drop of the lamps), when VCC=24V, VL=2, and M=8, R1>; 138Ω In addition, in order to maintain a constant output current, Vout should also be set to>; 0.8V, So R1<; 240Ω In order to achieve good output characteristics of the chip while meeting the power consumption requirements, it is recommended to choose an appropriate intermediate value for R1.
9.3.    Input/output equivalent circuit

Ten,Conclusion

        CXLE87133BCE provides an ideal driving solution for professional LED lighting systems with its high integration, excellent grayscale performance, and strong protocol compatibility. Whether it's complex stage lighting or large-scale building lighting, this chip can meet design requirements with high reliability and consistency.1gQ嘉泰姆

If you need to obtain CXLE87133BCE samples, technical information or customized support, please visitJTM-IC official websiteLearn more information. We are committed to providing customers with one-stop lighting control solutions from chips to systems.1gQ嘉泰姆


Eleven,Download the relevant chip selection guide                     More similar products ...1gQ嘉泰姆

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