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Comprehensive Analysis and Application Guide for CXLE88155N LED Driver Chip with Keyboard Scanning

1、 Chip Overview

        CXLE88155N is a dedicated control chip that integrates LED display drivers and keyboard scanning functions. It is manufactured using CMOS technology and has high stability, strong anti-interference ability, and rich display control functions. The chip integrates MCU digital interface, data latch, LED driver circuit, and keyboard scanning module internally, suitable for various digital tubes or LED display devices, widely used in smart water heaters, microwave ovens, washing machines, air conditioners, induction cookers, set-top boxes, electronic scales, smart meters and other household and industrial equipment.sVi嘉泰姆

CXLE88155N supports multiple display modes (10 segments×); 7 to 13 segments× 4-digit), capable of driving up to 10× A 2-matrix keyboard with 8-level duty cycle adjustable brightness adjustment function, supporting three wire serial communication interfaces (CLK, STB, DIO), built-in RC oscillator and power on reset circuit, providing SOP24, SSOP24, and QSOP24 packaging forms to adapt to different space and power consumption requirements.sVi嘉泰姆

2、 Main characteristics

Display flexibility: Supports 10 segments× 7-digit, 11 segment× 6-digit, 12 segment× 5-digit, 13 segment× Multiple display modes including 4-digit displaysVi嘉泰姆

Keyboard scanning: Maximum support for 10× 2 matrix buttons, automatic scanning, no need for external MCU interventionsVi嘉泰姆

adjustable brightness8-level pulse width adjustment (1/16~14/16), suitable for different environmental brightness requirementssVi嘉泰姆

communication interfaceThree wire serial interface (CLK, STB, DIO), supporting data read/write and key readsVi嘉泰姆

Built in optimizationBuilt in reverse bias leakage optimization circuit to avoid LED dimming problemssVi嘉泰姆

strong anti-interferenceSuitable for strong interference environments such as induction cookerssVi嘉泰姆

Diverse packaging optionsSOP24, SSOP24, QSOP24 are optional and suitable for high-density PCB layoutsVi嘉泰姆

3、 Detailed explanation of pin functions

symbol

pin name

Pin number

Instructions

DIO

Data output input

one

Input serial data on the rising edge of the clock, starting from the lower bits. Output serial data on the falling edge of the clock, starting from the lower bits. When outputting, it is an N-tube open leak output

CLK

Clock input

two

Read serial data on the rising edge and output data on the falling edge.

STB

Film selection input

three

Initialize the serial interface at the falling edge and then wait for the instruction to be received. The first byte after the low value of STB is used as an instruction, and when processing the instruction, other current processing is terminated. When STB is high, CLK is ignored.

K1～K2

Key scan signal input

4~5

The data input for this foot is latched after the display cycle ends

SGE1/KS1～ SEG10/KS10

Output (segment)

7~16

Segment output (also used as key scan output), P-tube open leak output

GRID1～ GRID4

Output (bit)

24~23sVi嘉泰姆 21~20

Bit output, N-tube open leak output

SEG12/GRID7 ～sVi嘉泰姆 SEG14/GRID5

Output (segment/bit)

19~17

Segment/bit multiplexing output, can only select segment or bit output

VDD

Logic power supply

six

Connect the power supply positively

GND

Logically speaking

twenty-two

Grounding system

4、 Detailed Explanation of Instruction System

CXLE88155N achieves display and key control through four instructions:sVi嘉泰姆

4.1. Display mode setting (B7 B6=00)

4.2. Data command settings (B7 B6=01)

4.3. Display control command (B7 B6=10)

Control the display switch and brightness adjustment.   sVi嘉泰姆
           MSB                                                LSBsVi嘉泰姆

4.4. Address command setting (B7 B6=11)

Set the starting address (C0H~CDH) of the display register, totaling 14 bytes.sVi嘉泰姆

5、 Display and keyboard scanning function

5.1. Display driver

5.1.1) Common cathode digital tubeSEG is connected to the anode, GRID is connected to the cathode, and segment selection is controlled by writing video memory data.sVi嘉泰姆

sVi嘉泰姆

      Figure 7 shows the schematic diagram of the connection of the common cathode digital tube. If the digital tube displays“ 0” Just need to open from the lower bits to the C0H (GRID1) addresssVi嘉泰姆
Just start writing 0x3F data. At this point, 00H corresponds to the data of each SEG1-SEG8 as shown in the table below.sVi嘉泰姆

5.1.2) Common anode digital tubeAn external PNP or MOS transistor is required for level conversion, and the GRID control bit is selected.sVi嘉泰姆
sVi嘉泰姆
        Figure 8 shows the schematic diagram of the connection of the Gongyang digital tube. If the digital tube displays“ 0” To address units C0H (GRID1), C2H (GRID2)sVi嘉泰姆
Write data 01H in C4H (GRID3), C6H (GRID4), C8H (GRID5), and CAH (GRID6) respectively, and write data in all other address CCH (GRID7) unitssVi嘉泰姆
According to 00H, the data corresponding to each SEG1-SEG8 is shown in the table below.sVi嘉泰姆

AttentionAfter power on, the content of the video memory is random. It is recommended to write 0x00 to all C0H~CDH for clearing to avoid garbled characters.sVi嘉泰姆

5.2. Keyboard scanning

Maximum support for 10× 2 matrix buttons, automatic scanning, completed every 2 display cycles.sVi嘉泰姆
sVi嘉泰姆
The storage address for key scan data is shown below. First, send the read key command, and then start reading 5-byte key data BYTE1— BYTE5, Read data from low ordersVi嘉泰姆
Start outputting, where B7 and B6 bits are invalid bits and the fixed output is 0. When the key corresponding to the K and KS pins of the chip is pressed, the BIT bit in the corresponding bytesVi嘉泰姆
For 1.sVi嘉泰姆

To read a button, send a read command and sequentially read 5 bytes of data (BYTE1~BYTE5), with each byte corresponding to 2 button states.sVi嘉泰姆
▲ Attention:1. CXLE88155N can read up to 5 bytes and does not allow multiple reads.sVi嘉泰姆
2. Read data bytes can only be read sequentially from BYTE1-BYTE5 and cannot be read across bytes. For example, hardware K2 corresponds to KS10sVi嘉泰姆
When the button is pressed, in order to read the data of this button, it is necessary to read the 5th bit of the 5th byte before reading the data.sVi嘉泰姆

5.2.2)Key scanning:It is recommended to design composite buttons on the same KS line, different K lines, or in series with diodes to avoid short circuits.sVi嘉泰姆
Key scanning is automatically completed by CXLE88155N and is not controlled by the user. Users only need to read key values in chronological order. Complete a key oncesVi嘉泰姆
Scanning requires 2 display cycles, and one display cycle takes approximately T=4ms. Within 8ms, 2 different keys were pressed successively, and the key values read twice were firstsVi嘉泰姆
The key value of the pressed button.sVi嘉泰姆
In the 7-bit 10 segment mode, the waveforms of SEG1/KS1 to SEG10/KS10 during keyboard scanning of the IC are shown in Figure (10):sVi嘉泰姆
sVi嘉泰姆
As shown in Figure (10), the internal button scanning principle of the chip is as follows: the chip gradually scans from SEG1/KS1 to SEG10/KS10, andsVi嘉泰姆
SEG1/KS1-SEG8/KS8 will be completed within one cycle, while SEG9/KS9-SEG10/KS10 will be completed in the next cycle. When sending a read button command, ifsVi嘉泰姆
The high level scan of the SEG1/KS1-SEG10/KS10 buttons is introduced into the K1/K2/K3 pins through the buttons, and the chip will recognize the high level internally and read 5sVi嘉泰姆
When the key data is one byte, the corresponding BIT bit will be set high.sVi嘉泰姆
▲ Attention:The display period is related to the oscillation frequency of the IC operation, and the oscillation frequency is not completely consistent. The above data is for reference only, and actual measurements shall prevail.sVi嘉泰姆
5.2.3) Key reuse:The issue with composite buttons: SEG1/KS1-SEG10/KS10 is a combination of display and button scanning. As shown in Figure (12)sVi嘉泰姆
For example, to display D1 on and D2 off, SEG1 needs to be set to“ 0” , SEG2 is“ 1” If S1 and S2 are simultaneously pressed, it is equivalent to SEG1 and SEG2sVi嘉泰姆
Short circuited, both D1 and D2 are illuminated.sVi嘉泰姆

sVi嘉泰姆
Solution:sVi嘉泰姆
1. In terms of hardware, the keys that need to be pressed simultaneously can be set on different K-lines as shown in Figure (13),sVi嘉泰姆

sVi嘉泰姆

2. The series diode is shown in Figure (14).sVi嘉泰姆

sVi嘉泰姆
▲ Note: It is recommended to use the same KS but different K keys as composite keys.sVi嘉泰姆

6、 Communication timing and data transmission

6.1. Serial Data Transmission Format:sVi嘉泰姆
Reading and receiving one BIT are both performed on the rising edge of the clock.sVi嘉泰姆
sVi嘉泰姆
▲ Attention:1. When reading data, an equal interval is required between setting instructions from the 8th rising edge of the serial clock CLK and reading data from the falling edge of CLKsVi嘉泰姆
Wait for Twait (minimum 2μ S). Please refer to the timing characteristic table for specific parameters.

6.2. Write data flow (address auto increment mode)

Using the address auto increment mode, setting the address is actually setting the starting address for storing the transmitted data stream. The starting address command word has been sent,sVi嘉泰姆
“ STB” There is no need to set the height to closely follow the data transmission, up to 14BYTE, and only after the data transmission is completed will it be sent; STB” Set high.sVi嘉泰姆
sVi嘉泰姆
Command1: Set Display ModesVi嘉泰姆
Command2: Set Data CommandsVi嘉泰姆
Command3: Set Display AddresssVi嘉泰姆
Data1~n: Transfer display data to Command3 address and subsequent addresses (up to 14 bytes)sVi嘉泰姆
Command4: Display control commands

▲ STB falling edge beginssVi嘉泰姆

▲ Send display mode commandsVi嘉泰姆

▲ Send data command (automatic address)sVi嘉泰姆

▲ Sending starting addresssVi嘉泰姆

▲ Continuously write up to 14 bytes of datasVi嘉泰姆

▲ STB rising edge endssVi嘉泰姆

6.3. Read button process

        Using the fixed address mode, setting the address is actually setting the address where the 1BYTE data to be transmitted is stored. The address has been sent,“ STB”sVi嘉泰姆
No need to set it high, immediately transmit 1BYTE data, and only after the data transmission is completed will it be sent; STB” Set high. Then reset the address where the second data needs to be stored,sVi嘉泰姆
Up to 14BYTE data transmission completed,“ STB” Set high.sVi嘉泰姆
sVi嘉泰姆
Command1: Set Display ModesVi嘉泰姆
Command2: Set Data CommandsVi嘉泰姆
Command3: Set Display Address 1sVi嘉泰姆
Data1: Transfer display data from address 1 to Command3sVi嘉泰姆
Command4: Set Display Address 2sVi嘉泰姆
Data2: Transfer display data 2 to Command4 addresssVi嘉泰姆
Command5: Display Control Commands

▲ Send read button command (42H)sVi嘉泰姆

▲ Waiting for Twait (≥ 2μ s)sVi嘉泰姆

▲ Read 5-byte key data sequentiallysVi嘉泰姆

6.4. Read button timing sequencesVi嘉泰姆

sVi嘉泰姆
Command1: Set the read button commandsVi嘉泰姆
Data1-5: Read key datasVi嘉泰姆

6.5. Program design flowchart using address auto increment and fixed address methods:sVi嘉泰姆

6.5.1) Program design flowchart using automatic address plus one:sVi嘉泰姆
sVi嘉泰姆
6.5.2) Flowchart of program design using fixed addresses:sVi嘉泰姆
sVi嘉泰姆

7、 Hardware design suggestions

▲power supply filteringConnect a 47 μ F electrolytic capacitor and a 104 ceramic capacitor in parallel between VDD and GND, and place them as close to the chip as possible.sVi嘉泰姆

▲Communication protectionConnect 100&Omega in series on DIO, CLK, and STB lines; Resist and parallel 100pF capacitor to ground to suppress interference.sVi嘉泰姆

▲driving voltageIf using a blue LED (with a voltage drop of about 3V), it is recommended to supply a voltage of 5V.sVi嘉泰姆

▲Anti interference designReduce communication frequency and strengthen power and ground shielding in strong interference environments.sVi嘉泰姆

8、 Summary of Electrical Parameters

8.1. Limit parameters (Ta=25 ℃, VSS=0V)

parameter

symbol

scope

unit

Logic power supply voltage

VDD

-0.5 ～+7.0

V

Logic input voltage

VI1

-0.5 ～ VDD + 0.5

V

LED SEG driver output current

IO1

-50

mA

LED GRID driver output current

IO2

+200

mA

power loss

PD

four hundred

mW

Operating Temperature

Topt

-40 ～ +85

℃

Storage temperature

Tstg

-65 ～+150

℃

8.1. Normal operating range (VSS=0V)

parameter

symbol

minimum

typical

maximum

unit

test conditions

Logic power supply voltage

VDD

three

five

six

V

-

High level input voltage

VIH

0.7 VDD

-

VDD

V

-

Low level input voltage

VIL

0

-

0.3 VDD

V

-

8.3. Electrical characteristics (VDD=5V, VSS =0V)

parameter

symbol

minimum

typical

maximum

unit

test conditions

High level output current

Ioh1

twenty

thirty-five

sixty

mA

SEG1～SEG10, Vo = VDD -3V

Low level input current

IOL

eighty

one hundred and twenty

-

mA

GRID1～GRID7 Vo=0.3V

Low level output current

Idout

three

-

-

mA

Vo = 0.4V,Dout

Allowable high-level output current

Itolsg

-

-

five

%

Vo = VDD – 3V, SEG1～SEG11

High level input voltage

VIH

zero point sevensVi嘉泰姆 VDD

-

V

CLK,DIO,STB

Low level input voltage

VIL

-

-

zero point threesVi嘉泰姆 VDD

V

CLK,DIO,STB

8.4. Switching characteristics (VDD=5V)

parameter

symbol

minimum

typical

maximum

unit

test conditions

Transmission delay time

tPLZ

-

-

three hundred

ns

CLK → DOUTsVi嘉泰姆 CL = 15pF, RL = 10K Ω

tPZL

-

-

one hundred

ns

rise time

tTZHone

-

-

two

μs

CL=300pF

SEG1～SEG10

tTZHtwo

-

-

zero point five

μs

GRID1～GRID4 SEG12/GRID7～ SEG14/GRID5

fall time

tTHZ

-

-

one point five

μs

CL = 300pF,SEGn,GRIDn

Maximum input clock frequencyrate

Fmax

-

-

one

MHz

Duty cycle 50%

Input capacitor

CI

-

-

fifteen

pF

-

8.5. Timing Characteristics (VDD=5V)

parameter

symbol

minimum

typical

maximum

unit

test conditions

Clock pulse width

PWCLK

five hundred

-

-

ns

-

Select pulse width

PWSTB

one

-

-

μs

-

Data establishment time

tSETUP

one hundred

-

-

ns

-

Data retention time

tHOLD

one hundred

-

-

ns

-

CLK → STB time

tCLK-STB

one

-

-

μs

CLK↑ → STB↑

8.6. Time series waveform diagram:sVi嘉泰姆

▲Working Voltage：3.0V ~ 6.0VsVi嘉泰姆

▲SEG pulling current: 35mA (typical value, Vo=VDD-3V）sVi嘉泰姆

▲Grid current injection120mA (typical value, Vo=0.3V）sVi嘉泰姆

▲Operating Temperature：-40℃ ~ +85℃sVi嘉泰姆

▲Maximum clock frequency：1MHzsVi嘉泰姆

9、 Package size

▲SOP24：15.34mm × 7.52mmsVi嘉泰姆

▲SSOP24：8.15mm × 5.35mmsVi嘉泰姆

▲QSOP24：8.63mm × 4.00mmsVi嘉泰姆

10、 Application circuit:

10.1. CXLE88155N Driver Common Negative Digital Screen Hardware Circuit Diagram (18):

10.2. CXLE88155N Driver Common Yang Digital Screen Hardware Circuit Diagram (19):sVi嘉泰姆

11、 Summary

        CXLE88155N is a comprehensive and simple interface LED driver and keyboard scanning integrated chip, especially suitable for multi digit digital display and key control needs in home appliances, industrial control and other fields. Its flexible instruction set, powerful anti-interference ability, and multiple packaging options make it an ideal choice for high reliability display driver solutions.sVi嘉泰姆

If you need the latest data manual or technical support, it is recommended to contact the official or authorized agent to obtain updated information.sVi嘉泰姆

TwelveSelection Guide for Related Chips;                        More similar products ....sVi嘉泰姆

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