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首页 > Products > Power Management > Regulator > DDR terminal voltage regulator >The CXTP65153 is a high performance linear regulator designed to provide power for termination of a DDR memory bus It significantly reduces parts count board space and overall system cost
The CXTP65153 is a high performance linear regulator designed to provide power for termination of a DDR memory bus It significantly reduces parts count board space and overall system cost

The CXTP65153 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The CXTP65153 contains a high-speed operational amplifier to provide excellent response to load transients. The CXTP65153 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for chipset and DIMMs. An additional feature found on the CXTP65153is an active low shutdown (SD) pin. When SD is pulled low the VTT output will Tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. The CXTP65153 used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses. A typical DDR memory system is seen in Figure 1.

The CXTP65153 is a high performance linear regulator designed to provide power for termination of a DDR memory bus It significantly reduces parts count board space and overall system cost
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1.产品概述       2.产品特点     f9O嘉泰姆

3.应用范围       4.技术规格书下载(PDF文档)f9O嘉泰姆

5.产品封装       6.电路原理图  f9O嘉泰姆

7.相关产品f9O嘉泰姆

   产品概述 返回TOPf9O嘉泰姆

CXTP65153是一款为DDR内存总线的终端提供电源而专门设计的高性能线性稳压器,同以往开关型解决方案相比,它大大减少了外围器件的个数和占用的PCB空间,并降低了系统的整体成本。CXTP65153的高速运算放大器对负载具有快速优良的瞬态响应,CXTP65153还采用了VSENSE pin以达到优越的负载调整率;CXTP65153采用VREF输出为chipset和DIMMs提供基准电压。CXTP65153的另外一个特点是设计了低电压有效关断pin SD,当SD被拉低时,VTT的输出将处于高阻状态;但VREF依然保持在有效状态,在这种状态下,芯片因为其低的静态电流而功耗减小。CXTP65153利用与串联终端电阻连接的方式为高速传输线的有源终端结构提供优良的电压源。The CXTP65153 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The CXTP65153 contains a high-speed operational amplifier to provide excellent response to load transients. The CXTP65153 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for chipset and DIMMs. An additional feature found on the CXTP65153is an active low shutdown (SD) pin. When SD is pulled low the VTT output will Tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. The CXTP65153 used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses. A typical DDR memory system is seen in Figure 1.

   产品特点 返回TOPf9O嘉泰姆


•非常低的静态电流(305μA)f9O嘉泰姆

•快速瞬态响应时间f9O嘉泰姆

•可为DDR-Ⅰ和DDR-Ⅱ的终端电压提供/吸收1.5A的电流f9O嘉泰姆

•为其他内存提供基准输出和控制电路f9O嘉泰姆

•低电流关断模式f9O嘉泰姆

•过温保护f9O嘉泰姆

•全负载高精度输出电压f9O嘉泰姆

•很少的外围器件f9O嘉泰姆

•SOP-8、SOP(EP)的封装f9O嘉泰姆

•符合RoHS规范和100% Pb-freef9O嘉泰姆

z Extremely low quiescent current (305uA) f9O嘉泰姆

z Fast transient response time f9O嘉泰姆

z Capable of sourcing and sinking 1.5A for DDR-I termination f9O嘉泰姆

z Reference out for other memory and control components f9O嘉泰姆

z Low-current shutdown mode f9O嘉泰姆

z Over-temperature protection f9O嘉泰姆

z High accuracy output voltage at full-load z Low external component count f9O嘉泰姆

z Available in SOP-8, SOP(FD) package f9O嘉泰姆

z RoHS compliant and 100% lead (Pb)-freef9O嘉泰姆

   应用范围 返回TOPf9O嘉泰姆


• DDR-I 及 DDR-II 终端电压f9O嘉泰姆

z DDR-I and DDR-II termination voltagef9O嘉泰姆

   技术规格书(产品PDF) 返回TOP f9O嘉泰姆


     需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持f9O嘉泰姆

 QQ截图20160419174301.jpgf9O嘉泰姆

产品封装图 返回TOPf9O嘉泰姆


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电路原理图 返回TOPf9O嘉泰姆


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DDR终端稳压器f9O嘉泰姆

Part   Numberf9O嘉泰姆

remarkf9O嘉泰姆

Iout (A)f9O嘉泰姆

Vin (V)f9O嘉泰姆

Vout (V)f9O嘉泰姆

Output Voltage Accuracy (mV)f9O嘉泰姆

Shutdownf9O嘉泰姆

Packagef9O嘉泰姆

CXTP65153f9O嘉泰姆

1.5A DDR Termination Regulatorf9O嘉泰姆

± 1.5f9O嘉泰姆

1.8 ~ 5.5f9O嘉泰姆

0.9~1.25f9O嘉泰姆

± 20f9O嘉泰姆

Yesf9O嘉泰姆

SOP-8 (EP)f9O嘉泰姆

CXTP65154f9O嘉泰姆

2A Sink/Source Bus Termination Regulatorf9O嘉泰姆

± 2f9O嘉泰姆

1.8 ~ 5.5f9O嘉泰姆

0.9~1.25f9O嘉泰姆

± 20f9O嘉泰姆

Yesf9O嘉泰姆

SOP-8 (EP)f9O嘉泰姆

CXTP65155f9O嘉泰姆

Sink/Source DDR Termination Regulatorf9O嘉泰姆

± 2f9O嘉泰姆

2.375 ~ 5.5f9O嘉泰姆

0.5~1.8f9O嘉泰姆

± 25f9O嘉泰姆

Yesf9O嘉泰姆

TDFN-10,SOP-8f9O嘉泰姆

CXTP65156f9O嘉泰姆

DDR Termination Regulatorf9O嘉泰姆

± 1.5f9O嘉泰姆

1.5~3.3f9O嘉泰姆

0.75~0.9f9O嘉泰姆

±20f9O嘉泰姆

Yesf9O嘉泰姆

SOP-8(EP)f9O嘉泰姆