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1.产品概述       2.产品特点     AfY嘉泰姆

3.应用范围       4.技术规格书下载（PDF文档）AfY嘉泰姆

5.产品封装       6.电路原理图  AfY嘉泰姆

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   产品概述 返回TOPAfY嘉泰姆

The CXEP3475 CXEP3475B is a linear regulator designed to meet the JEDEC SSTL-18, SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR I/II/III/IIIL -SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 3A continuous current in the application such as required for DDR I/II/III /IIIL SDRAM termination. The CXEP3475 CXEP3475B can easily provide the accurate VTT voltage with two external resistors generating reference voltage. The quiescent current is as low as 750μA @ VCNTL = 3.3V. So the power consumption can meet the low power consumption applications. The CXEP3475 CXEP3475B also has a shutdown function by setting VREF smaller than 0.2V, that provides Suspend to RAM (STR) functionality. When in the shutdown mode, the VTT output (on VOUT pin) will be tri-state providing a high impendence. A power saving advantage can be obtained in this mode through lowering the quiescent current to 50μA @ VCNTL = 3.3V.

   产品特点 返回TOPAfY嘉泰姆

„ Support DDR I (1.25 VTT), DDR II (0.9 VTT), DDR III (0.75 VTT), DDR IIIL (0.675VTT) and DDR IV (0.6 VTT) Requirements AfY嘉泰姆

„ VCNTL Supply Voltage: 3V to 5.5V AfY嘉泰姆

„ Termination Supply Voltage : 1.2V to 3.6V AfY嘉泰姆

„ Stable with Output Ceramic Capacitor AfY嘉泰姆

„ Over Current Protection AfY嘉泰姆

„ Thermal Shutdown Protection AfY嘉泰姆

„ Shutdown Function for STR (S3) Mode AfY嘉泰姆

„ Adjustable Output Voltage with Resistors AfY嘉泰姆

„ Built-In Soft-Start AfY嘉泰姆

„ Power MOS integrated AfY嘉泰姆

„ SOP-8 (FD) and MSOP-8 (FD) Package AfY嘉泰姆

„ RoHS CompliantAfY嘉泰姆

   应用范围 返回TOPAfY嘉泰姆

„ DDR-SDRAM Termination Voltage AfY嘉泰姆

„ DDR I / DDR II / DDR III / DDR IIIL Termination Voltage AfY嘉泰姆

„ SSTL-18 AfY嘉泰姆

„ SSTL-2 AfY嘉泰姆

„ SSTL-3AfY嘉泰姆

   技术规格书（产品PDF) 返回TOP AfY嘉泰姆

     需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！AfY嘉泰姆

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产品封装图 返回TOPAfY嘉泰姆

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电路原理图 返回TOPAfY嘉泰姆

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◀ Previous:DDR Termination Regulator CXEP3474 is a linear regulator designed to meet the JEDEC SSTL (Series Stub Termination Logic) specifications in DDRI/II/III/IIIL/IV–SDRAM systems It provides accurate

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